Although FPGAs bring powerful capabilities and flexibility to embedded design, the additional development processes also introduce new complexities and limitations to the design work. Integrating traditional hardware-FPGA-software design processes and fully utilizing the reprogrammable features of FPGAs is one of our solutions.
As FPGA technology gradually extends to military electronic systems and almost all areas of the embedded electronics industry, applications that leverage the advantages of programmable logic have become mainstream. Communication, airborne, and control systems particularly benefit from the design flexibility, field reconfiguration, and parallel processing capabilities of FPGAs. Meanwhile, shorter design cycles and a more streamlined verification process help accelerate the deployment of applications in the field.
Despite the ubiquity of FPGAs, there are few applications that can truly harness the flexible design potential of FPGAs. This limitation arises largely because FPGA development has often been a simple overlay or, at best, an add-on to traditional hardware-software workflows. This isolated FPGA development phase can significantly increase the complexity of the overall design process, ultimately limiting the range of design options available in the hardware-software domain.
To simplify the overall design work and enrich design options, independent design processes such as hardware design, software development, and programmable hardware design need to be integrated and treated as a cohesive task. Only by allowing all design processes to share a unified design database and a common design environment at the foundational level can the primary unique advantage of FPGA reprogrammability be fully realized, pushing FPGA design to unprecedented levels. Understanding the trends and challenges faced in FPGA development is key to fully leveraging its flexibility, as well as mastering how to achieve coordinated integration among the three major design aspects in FPGA systems (hardware, programmable hardware, and software).
FPGA Development from Glue Logic to SoC
When FPGAs first entered the embedded market, they were seen as a convenient and effective alternative technology for implementing a large amount of simple glue logic. In such applications, embedded hardware is a subordinate part of the primary hardware-software design, and its development process does not involve the design processes of other components nor does it need to interact with them.
However, today’s FPGA devices and their usage have undergone significant changes based on the concept of convenient containers for massive digital logic. Large-capacity FPGAs can now accommodate entire SoC designs, where core functional elements such as processors, memory, and high-speed data processing are implemented in the programmable domain. In military embedded systems, due to the relatively low production volumes, it is challenging to adopt ASIC design solutions, while FPGAs provide an economical and feasible way to fully leverage the physical simplicity and reliability advantages of SoC design solutions.
One major difference between SoC implementation and simple glue logic design is that hardware and software development are now fundamentally related to and dependent on FPGA design. This is because FPGA devices and supporting peripherals are central and core elements of the physical design, and embedded application software must also be loaded onto the FPGA to function. Consequently, any changes in the FPGA domain will have significant impacts on the hardware and software domains.
Restricted Innovation
If we view the various components of hardware, software, and even current embedded hardware design as separate and unrelated tasks, the conventional development process for FPGA product design still adopts traditional methods, regardless of how interdependent the design domains are.
A change in one design domain often leads to destructive impacts on other domains and requires a time-consuming redesign. That is to say, significant decisions, such as locking in hardware-software partitioning, must be made (and locked) early in the design phase, which is no different from traditional non-FPGA embedded design. In fact, physical hardware such as FPGA devices and peripheral hardware, as well as subsequent programmable hardware elements, are sequentially locked in before meaningful software development can take place.
These initial decisions determine the parameters and limitations of subsequent development processes, so the options available for design become increasingly limited as the process progresses. For example, the selected FPGA device (and hardware peripherals) will define the performance ceiling, including determining which embedded IP to use, and the embedded hardware design subsequently defines the functions available for software. In other words, the FPGA device can only support the soft processors provided by the device vendor, which in turn defines the programming options available for application software.
Moreover, to fine-tune the performance of design solutions, such as transferring software algorithms to embedded hardware, switching from embedded processors to hardwired processors, or selecting different types of FPGAs, would require large-scale redesigns across all domains, including hardware, programmable hardware, and software. For military/aerospace systems with tight development timelines, such redesigns can significantly disrupt design cycles, leading most engineers to avoid such design risks at all costs. However, both high performance and design stability are equally critical, making it essential to examine processor options and fully leverage the advantages of soft algorithms over hard algorithms.
Rebuilding Integration
As mentioned earlier, simply adding FPGA development processes to existing design workflows is insufficient to fully realize the advantages of FPGAs. For applications that require reducing NRE costs and accelerating design speed, the limitations imposed by traditional design methods negate this advantage; this is precisely where FPGAs should play their biggest role.
The first step in restoring design choices and fully leveraging FPGA advantages is to unify hardware design, software development, and programmable hardware design. By utilizing an integrated design system and applications from a unified data model of overall design, design domains can interact and respond promptly to changes in designs across the domains. In practice, each domain uses a subset of the same design and component library data. Since changes can be easily (even automatically) reflected across all design domains, design changes can be significantly simplified, such as transferring functions between software and hardware or exploring other devices.
For instance, in a unified design data pool, the design data and configuration files for the selected FPGA device can simultaneously apply to both hardware and FPGA design domains. If the FPGA device or its pin configuration is changed during the FPGA design phase, that information will immediately be utilized in the implementation of hardware design. This way, exploring different design options becomes more effective, and advanced design functionalities such as pin swapping between hardware and FPGA design domains are also simplified.
Fully Utilizing Reprogrammability
In this integrated design environment, developers can finally fully leverage the flexibility of FPGAs. For example, in a typical environment, the majority of actual placement locations for physical hardware components can make connections between FPGAs and peripherals extremely complex, which is also a problem caused by high-density BGA packaging. One solution is to address the complexity of wiring between components within the FPGA itself, using the FPGA’s reconfigurable pins and internal wiring capabilities to strategically arrange the on-board connection lines.
We can solve the on-board wiring challenges using the pin reassignment and internal wiring capabilities of the FPGA, which can also potentially reduce board space usage and layer requirements. This concept also relies on a platform-level hardware and FPGA development environment, which is essential to support intelligent and automatic pin swapping between hardware and FPGA domains.
Moreover, this integrated design approach also makes it possible to implement global software systems that can enhance the abstraction level of the design process, such as using diagrammatic or graphical embedded design methods to synchronize hardware and software domains. Since data already exists as a unified entity throughout all domains of the integrated design environment, unlike systems that employ a series of independent tools, higher-level design abstractions in a single domain do not complicate the design data flow.
The natural extension of this design abstraction is to implement a high-level embedded layer that effectively separates software elements from their associated hardware. These inserted layers standardize the interfaces between processors and other hardware (such as memory and peripherals), thus eliminating the need to consider the underlying hardware complexity issues associated with I/O configurations and bus systems. Whether performing traditional design updates, configuring different product modes, reusing existing IP, or executing post-production upgrades, reconfiguring FPGA designs will become a simpler and lower-risk process.
In practice, using the Wishbone bus architecture, library-based FPGA cores can simultaneously support processors and peripherals. By effectively “wrapping” devices to make them architecturally equivalent to other processors, these cores can extract processor interfaces, allowing modifications to processors as needed without affecting the peripherals connected to them or necessitating significant changes to the design solution. Besides FPGA-based “soft” devices, this concept can also be extended to hybrid hard-core processors, external processors, and off-chip independent peripheral and memory devices.
Next-Generation FPGA Design
The integrated high-level design approach introduced in this article is achieved through leveraging the reprogrammability of FPGA hosts. All layers and interfaces of applications, as well as the functional designs themselves, are automatically incorporated into the FPGA system. Therefore, unlike traditional processes applicable to “fixed” ASIC-like SoC designs, equivalent high-level FPGAs can dynamically explore different hardware design options without severely impacting other parts of the design solution.
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