The main instruction set architectures (ISA) of modern processors include: x86 instruction set architecture and RISC instruction set architecture.
-
CISC aims to complete tasks in one go, which is efficient but complex (high performance, high power consumption);
-
RISC breaks tasks down and completes them in steps, which requires less personal capability (lower performance, lower power consumption), but at the cost of lower efficiency.
Among them, x86 can be divided into x86-32 (Intel), x86-64 (Intel), and AMD64 (AMD). RISC can be divided into ARM, MIPS, Alpha, and RISC-V. Domestic CPUs have formed a development pattern in the Xinchuang market with “four technical paths (x86, ARM, MIPS, Alpha) and six major manufacturers (Zhaoxin, Haiguang, Kunpeng, Feiteng, Longxin, Shenwei).”
1. x86 Instruction Set
First, the x86 instruction set is designed to maintain binary compatibility, meaning applications from previous generations of chips can still run on next-generation chips, making previous and subsequent series of chips part of a “series machine”. This has led to the expansion of many new instructions, resulting in the constant growth of the x86 instruction set.
Second, the x86 instruction set adopts a strong instruction approach in its design, meaning one instruction can accomplish very powerful functionalities. For example, one instruction can complete the entire computation process across different memory locations, or move a piece of data directly from one memory location to another, and this powerful operation is completed in one clock cycle.
The above image lists the changes in the number of instructions according to Intel’s official statistics. Over nearly 40 years of development, x86 has grown from fewer than 200 instructions to over 1600 instructions today.
The above image shows the types of MOV instructions in the x86 instruction set, which can skip a series of lower-level micro-operations to achieve a more complex instruction functionality.
Based on the above design concepts, the x86 instruction set has the following advantages and disadvantages. Note that disadvantages may also be advantages, and advantages may also be disadvantages, which reflects the dialectical materialism of Marxism.
-
Due to the need to be compatible with historical versions, the hardware design of x86 is complex, which has become its historical burden. However, as the saying goes, “a blessing in disguise”, binary compatibility has gained strong support from IBM, allowing Intel to quickly dominate the PC and desktop market.
-
The functionality of a single instruction is strong, which lowers the requirements on the compiler. Furthermore, there is no need to consider so many lower-level instructions, making it easier for early assembly programmers to program in x86.
-
Multiple efficient instructions can be executed in parallel, making the performance of a single core powerful. Early processors with single-core architecture were sufficient to meet application needs.
-
A large number of redundant transistors are required to implement this CISC complex instruction set design. The redundant transistors bring significant area and power consumption overhead.
Today, the x86 instruction set has achieved a near-monopoly advantage in laptops, desktops, and servers, closely linked to IBM. It can be said that IBM’s choice has shaped the x86 instruction set’s current state and has made Intel, a once obscure company, successful.
The above two paragraphs are quoted from technews and Semiconductor Industry Observation, which briefly describe IBM’s early choices and their tremendous market success.
2. ARM Instruction Set
In the 1980s, computer scientists analyzed a large number of programs and found that 80% of the instructions were seldom used, while processors frequently used 20% of the instructions, such as Load instructions, conditional branch instructions, Store instructions, and comparison instructions. As shown in the table below, this table is cited from “Computer Architecture: A Quantitative Approach (6th Edition)” by David Patterson and John Hennessy.
For in-depth knowledge about ARM, please refer to the articles “Understanding ARM Processor Architecture and Ladder Diagram”, “Overview, Architecture, and Technical Introduction of ARM v8 Processors”, “Feiteng and Kunpeng: Domestic Arm Architecture CPU Servers are Rising”, “Collection: From Global Supercomputing Strategy to the Development of ARM Instruction Architecture in HPC”, “Detailed Explanation of Amazon’s Latest Arm Server Chip”, and “Transformation of Computing Chips: The Trend of ARM Replacing x86”.
As a result, early RISC instruction sets and MIPS instruction sets emerged, which removed a large number of infrequently used redundant instructions and retained only the most basic, commonly used, and simplest instruction sets. The processor architecture represented by this RISC instruction set is the ARM architecture, which launches three authorized versions with each generation to facilitate customization by different customers:
-
Cortex-A core, aimed at high-performance applications. -
Cortex-R core, aimed at real-time systems. -
Cortex-M core, aimed at embedded device scenarios.
Compared to the x86 instruction set (CISC complex instruction set), the changes in the ARM RISC instruction set mainly include:
First, a large number of redundant instructions and instructions retained for historical reasons have been removed based on statistical results.
Second, the original strong instruction in x86 is replaced by multiple basic simple instructions in ARM.
For example, the multiplication instruction provided by CISC can complete the multiplication of two numbers in memory a and memory b, storing the result in memory a, requiring multiple CPU cycles to complete; while RISC does not provide a “one-stop” multiplication instruction, it requires four single CPU cycle instructions to complete the multiplication of the two numbers: loading memory a into a register, loading memory b into another register, multiplying the numbers in the two registers, and storing the result back in memory a.
Based on the above design concepts, or under such underlying logic, the ARM instruction set processor architecture has the following advantages and disadvantages:
-
A large number of redundant hardware designs from x86 have been removed, making the design of DEC decoders simpler and saving a significant amount of area and power consumption overhead.
-
The functionality of a single ARM instruction is more singular and basic; this instruction can be referred to as a “weak instruction” compared to the strong instructions of x86, and the power consumption required to execute such weak instructions is further reduced.
-
Since what could be accomplished with one strong instruction in x86 requires multiple weak instructions in ARM, the design difficulty of the compiler is greatly increased, as well as the difficulty of programming in assembly language.
-
Due to the simpler hardware structure of ARM instruction set processors compared to x86 instruction set processors, a single ARM core has a smaller area and power consumption, but its performance is also weaker. This leads to the need to stack multiple weak ARM cores to match the performance of a powerful x86 core.
3. RISC-V Instruction Set
The RISC architecture has gone through four generations: RISC-I (1981), RISC-II (1983), RISC-III (1984), and RISC-IV (1988), but has never received the attention it deserved. However, during this process, the design philosophy of RISC has given rise to a series of new architectures such as MIPS, IBM PowerPC, and the currently dominating ARM in mobile edge computing.
For in-depth knowledge about RISC-V, please refer to articles such as “RISC-V Popular Science: Understanding Open Source ISA Architecture”, “Introduction and Practice of XuanTie RISC-V Processor”, “Report on the Development of Open Instruction Set and Open Source Chips (RISC-V and MIPS)”, “Clarification of Misunderstandings about RISC-V and Open Source Processors”, “In-Depth: RISC-V Instruction Set Architecture and Global Implementation”, “In-Depth: RISC-V Technology and Instruction Set Architecture”, and “In-Depth Report: RISC-V Architecture Analysis (50-page PPT)”.
In the early 21st century, influenced by the tremendous success of the open-source movement in operating systems and application software (such as Linux), a new prospect for open-source chip design emerged.
It is believed that RISC-V is expected to create the third wave of chip innovation after x86 and ARM. The flexibility of RISC-V and its support for customized and fragmented scenarios are good, so it is currently mainly applied in terminal fields such as the Internet of Things, but there have already been attempts in computers and servers. Important events in the development of RISC-V in China include:
-
In September 2018, the China RISC-V Industry Alliance was announced. -
In November 2018, the China Open Instruction Ecology (RISC-V) Alliance was announced, with Academician Ni Guangnan serving as the chairman of the alliance. -
In November 2018, the China Advisory Committee of the RISC-V Foundation was announced. -
In July 2019, Alibaba T-head released the high-performance XuanTie 910 RISC-V processor. -
In August 2019, GigaDevice released the world’s first 32-bit general-purpose MCU based on the RISC-V core. -
In March 2020, the foundation’s headquarters moved from the US to Switzerland, claiming to avoid political risks. -
In August 2023, the RISC-V China Summit opened in Beijing, attended by Academician Ni Guangnan of the Chinese Academy of Engineering and Calista Redmond, CEO of the RISC-V International Foundation. -
In November 2023, Alibaba T-head launched three XuanTie series processors based on the RISC-V architecture, which will soon be put into large-scale commercial use.
4. Summary of Instruction Sets
The relationship between these two instruction sets is akin to two different cooking styles. Some kitchens may prefer complex and diverse cooking methods, while others may prefer simple and efficient cooking methods. Similarly, CPU designers can choose to use either CISC or RISC instruction sets according to different needs to meet various application scenarios and performance requirements.
-
x86 Architecture: A closed architecture, firmly controlled by Intel and AMD, with AMD granting HG authorization for the Zen1 architecture; VIA (Taiwan’s VIA Technologies) once obtained the x86 architecture License authorization, later acquired by ZhiXin; for over 20 years, there has been no fourth authorized company, and other chip companies cannot use it either.
-
It is a mainstream architecture with a good ecosystem, but its closed state due to Intel and AMD’s monopoly has hindered the innovation process of domestic x86 CPU manufacturers, which are still primarily in the “digestion, absorption” and “small innovation” stage. However, its advantage lies in its compatibility with the existing x86 ecosystem like Wintel.
-
ARM Architecture: An open architecture, although owned by Arm Holdings, it is open for authorization and requires payment. Currently, H and F have permanent authorization for the ARM v8 architecture; domestic manufacturers like Alibaba T-head and ZTE have purchased ARM v9 architecture IP authorization.
-
It is a mainstream architecture with a relatively good ecosystem. The open authorization commercial model allows domestic ARM CPU manufacturers to innovate more freely, but it comes at a high cost. Whether to develop a domestic ARM v9 instruction set (entering the autonomous innovation stage) is currently unknown, but considerations will definitely be related to the ecosystem, and it may not have reached the stage of “decoupling” from the international ARM ecosystem, as the ARM ecosystem is rapidly catching up with x86.
-
MIPS Architecture: An open architecture, currently the R6 version of the MIPS instruction set has been opened up, managed by Wave Computing, but it is difficult to reverse its decline, and it has finally announced the termination of development and joined the RISC-V Foundation. LX was initially based on the MIPS architecture for authorization and later derived the LoongArch autonomous architecture.
-
It is a niche architecture with a weak ecosystem, and with Wave Computing’s parent company “defecting” to join the RISC-V Foundation, domestic CPU manufacturers have no choice but to embark on the “independent innovation” stage, directly sacrificing the already thin MIPS ecosystem. While independent innovation is certainly valuable, it requires rebuilding an independent ecosystem, which is a long and arduous task.
-
Alpha Architecture: An open architecture, currently there is no entity asserting rights to this instruction set, but related patents have been divided among HP, Intel, etc. Shenwei was initially based on the Alpha architecture and later derived the SW64 autonomous architecture.
-
It is a niche architecture with a weak ecosystem, and since it has long been without a “parent” (no entity company operating), it is natural for domestic CPU manufacturers to choose “independent innovation”! While independent innovation is certainly valuable, the thin ecosystem means it can only be implemented in niche markets.
-
RISC-V Architecture: An open-source architecture, the most unique, not belonging to any institution or country, open-source and free to use, with operational costs relying entirely on the support of the foundation’s associates. Led by Alibaba T-head, more and more startups are joining the RISC-V architecture camp.
Disclaimer:Thank you to the original author for their hard work. All articles reprinted by this account will be noted in the text. If there are any copyright issues, please contact us for resolution.
Warm Reminder:
Scan theQR code to follow our public account, clickRead Original link to obtain “Complete Technical Data Package for Architects (All)”e-book data details.
