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The main instruction set architectures (ISA) of modern processors include: x86 instruction set architecture, RISC instruction set architecture.
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CISC tries to complete tasks in one go, efficient but brain-intensive (high performance, high power consumption);
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RISC breaks down tasks and completes them in stages, although it requires less personal ability (low performance, low power consumption), the cost is lower efficiency.
Among them, x86 can be divided into x86-32 (Intel), x86-64 (Intel), AMD64 (AMD), etc. RISC can be divided into ARM, MIPS, Alpha, RISC-V. Domestic CPUs have formed a development pattern in the Xinchuang market with “four technical paths (x86, ARM, MIPS, Alpha), and six major manufacturers (Zhaoxin, Haiguang, Kunpeng, Feiteng, Longxin, Shenwei)”.
1. x86 Instruction Set
First, the x86 instruction set maintains binary compatibility, meaning: applications from the previous generation of chips can still run on the next generation of chips, making previous and subsequent series of chips a “series machine”, expanding many new instructions, leading to the continuous expansion of the x86 instruction set scale.
Second, the x86 instruction set adopts a strong instruction approach during design, meaning: one instruction can complete very powerful functions. For example, one instruction can complete the entire computation process at different memory locations, or move a piece of data directly from one location in memory to another, and this powerful operation is completed within one clock cycle.
The above image lists the number of instructions changes officially counted by Intel. In nearly 40 years of development history, the x86 instruction set has grown from less than 200 instructions to over 1600 instructions today.
The above image lists the types of MOV instructions in the x86 instruction set, which can skip a series of low-level micro-operations to achieve a more complex instruction function.
Based on the above design philosophy, the x86 instruction set has the following advantages or disadvantages. Note that disadvantages may also be advantages, and advantages may also be disadvantages, which is the dialectical materialism of Marx.
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Due to the need to be compatible with past historical versions, the hardware design of x86 is complex, which has become its historical burden. However, as the saying goes, “A blessing in disguise”, binary compatibility has received strong support from IBM, allowing Intel to quickly occupy the PC and desktop market.
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The strong function of one instruction reduces the requirements for compilers. Additionally, there is no need to consider so many low-level instructions, early assembly programmers faced with x86 programming were relatively relaxed.
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Multiple high-efficiency instructions running in parallel make the performance of a single core powerful. Early processors with single-core architecture were sufficient to meet application needs.
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It is necessary to have a large number of redundant transistors to achieve this CISC complex instruction set design. Redundant transistors bring a lot of area and power consumption overhead.
Today, the x86 instruction set has achieved a near-monopoly advantage in scenarios such as laptops, desktops, and servers, and has a close relationship with IBM. It can be said that IBM’s choice has created the x86 instruction set’s present and has made Intel, a once obscure small company, successful.
The above two paragraphs are quoted from technews and Semiconductor Industry Observation, which briefly describe IBM’s early choices and their huge market success.
2. ARM Instruction Set
In the 1980s, computer scientists analyzed a large number of programs and found that 80% of instructions were rarely used, while processors frequently used the 20% of instructions, such as Load instructions, conditional branch instructions, Store instructions, and comparison instructions. The table below is quoted from “Computer Architecture: A Quantitative Approach (6th Edition)”. The authors are David Patterson and John Hennessy.
For in-depth knowledge about ARM, please refer to the articles “Analysis of ARM Processor Architecture and Ladder Diagram”, “Overview of ARM v8 Processor, Architecture, and Technology Introduction”, “Feiteng Series and Kunpeng Series: Domestic Arm Architecture CPU Servers are Rising”, “Collection: From Global Supercomputing Strategy to ARM Instruction Architecture Development in HPC Field”, “Detailed Explanation of Amazon’s Latest Arm Server Chip”, and “Revolution in Computing Chips: ARM Replacing x86 as a Trend”, etc.
Therefore, the early RISC instruction set and MIPS instruction set emerged, which eliminated a lot of rarely used redundant instructions and retained the most basic, commonly used, and simplest instruction set. The representative processor architecture based on this RISC instruction set design is the ARM architecture, which launches the following three authorized versions for different customers’ customization:
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Cortex-A core, aimed at high-performance applications. -
Cortex-R core, aimed at real-time systems. -
Cortex-M core, aimed at embedded device scenarios.
Compared to the x86 instruction set (CISC complex instruction set), the changes in the ARM RISC instruction set are mainly:
First, a large number of redundant instructions and historically compatible instructions have been deleted based on statistical results.
Second, the original strong instruction of x86 is replaced by multiple basic simple instructions in ARM.
For example: The multiplication instruction provided by CISC can complete the multiplication of two numbers in memory a and memory b and store the result in memory a, requiring multiple CPU cycles to complete; while RISC does not provide a “one-stop” multiplication instruction, it needs to call four single CPU cycle instructions to complete the multiplication: load memory a into the register, load memory b into the register, multiply the two numbers in the registers, and store the result in memory a.
Based on the above design philosophy, or rather, under such underlying logic, the processor architecture of the ARM instruction set has the following advantages or disadvantages:
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Eliminating a large number of x86 redundant hardware designs makes the design of DEC decoders simpler, saving a lot of area and power consumption overhead.
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One ARM instruction’s function is more single and basic, and this instruction can be called a