Introduction
Having been involved in embedded software development for nearly five years, I have predominantly used microcontrollers from the ARM Cortex M series. During this period, I have been grateful for the presence of C language compilers, which allowed me to develop without needing to delve into assembly language. However, I feel I have missed out on some aspects of the beauty of compilers and CPUs, so I decided to spend my weekends exploring the wonders of the ARM CPU architecture and the secrets of C language compilers through research and experimentation. (I personally disagree with the teaching methods of microcomputer principles courses in schools).
-
Exploration of ARM | 1. Introducing the ARM Cortex-M Family
1. ARM Instruction Set Architecture
The ARM instruction set architecture, abbreviated as ISA, supports three instruction sets: A64, A32, and T32.
-
The A64 instruction set is used in Armv8-A to support 64-bit architecture -
The A32 instruction set, found in Armv6 and Armv7 architectures, is referred to as the ARM instruction set -
The T32 instruction set, also in Armv6 and Armv7 architectures, is known as the Thumb instruction set
A32 Instruction Set
The A32 instruction set, prior to armv8, is also known as “the ARM instruction set, with a fixed instruction length of 32 bits and 4-byte alignment”.
T32 Instruction Set
The T32 instruction set, prior to armv8, is known as the Thumb instruction set.
Initially, the ARM instruction set had a fixed length of 32 bits. To improve code density, “the Thumb instruction set was designed as a 16-bit instruction set”, allowing developers to use both the ARM and Thumb instruction sets to reduce code size. However, these are two separate instruction sets with two operating states, requiring frequent switching between ARM and Thumb states, which can be cumbersome.
Over time, with the introduction of Thumb-2 technology, “most functions of the ARM instruction set were incorporated into the Thumb instructions, evolving the Thumb instruction set into a mixed-length instruction set of 16 and 32 bits, known as the Thumb-2 instruction set”.
The advent of the Thumb-2 instruction set allows compilers to balance performance and code size within a single instruction set, providing excellent code density while minimizing system memory size and cost.
2. ARM Architecture Extensions
ARM also offers a series of architecture extensions to meet the demands of next-generation processors, providing new functionalities to ARM processors. 
DSP Extension
The DSP for Cortex-M provides high-performance “signal processing capabilities” for ARM Cortex-M processors, applicable in scenarios such as audio, sound, sensor hubs, and machine learning, without the need for additional DSP devices.
Processors with DSP extensions include Cortex-M4, Cortex-M7, Cortex-M33, Cortex-M35P, and Cortex-M55.
The DSP extension instructions are added on top of the Thumb instruction set and optional floating-point units, maintaining the usability of the original Cortex-M programming model while adding digital signal processing capabilities.
SIMD Instructions
These Cortex-M processors with DSP extensions also provide “SIMD instructions” to operate on 8-bit or 16-bit integers.
SIMD stands for Single Instruction Multiple Data, allowing “SIMD instructions to simultaneously operate on 2 16-bit values or 4 8-bit values” while all registers remain 32 bits. 
Instructions operating on 8-bit or 16-bit data are particularly useful for processing video or audio data, as these do not require a 32-bit width. SIMD instructions provide the capability to process this data in parallel.
Floating-Point Unit
The ARM floating-point unit technology provides high performance and efficiency hardware support for “half-precision, single-precision, and double-precision floating-point operations”.
The ARM floating-point unit is fully compatible with the IEEE-754 standard, making it particularly suitable for applications requiring high precision in floating-point calculations.
Applications for floating-point data types include:
-
Automotive control programs -
3D graphics -
Industrial control systems -
Motion control systems
Helium
The ARM Helium technology is a vector extension for the ARM Cortex-M processor series, referred to as MVE, and is an extension of the Armv8.1-M architecture, providing significant performance improvements for machine learning applications in small embedded devices.
The Cortex-M55 is the first processor to feature this extension.
The Helium technology adds over 150 new scalar and vector instructions, enabling efficient computation of 8-bit, 16-bit, and 32-bit fixed-point data. The 16-bit and 32-bit fixed-point formats are widely used in traditional signal processing, such as audio processing, while the 8-bit fixed-point format is crucial in machine learning applications, such as neural network computations and image processing.
Similarly, Helium also supports floating-point data types, including single-precision (32-bit) and half-precision (16-bit) floating-point numbers.
3. What Instruction Set Does Cortex-M Use?
Having discussed the basic instruction set and extended instruction set of ARM, it is time to answer our initial question: What instruction set does ARM Cortex-M use?
“The entire ARM Cortex-M series only supports a single instruction set: the Thumb instruction set or the Thumb-2 instruction set. Specifically, it supports the T32 instruction set.”
Among the many members of the Cortex-M family, the support for the Thumb/Thumb-2 instruction set varies by processor, with “most processors supporting a subset of the Thumb/Thumb-2 instruction set”.
The support for the Thumb instruction set in the Cortex-M0, Cortex M3, Cortex M4, and Cortex M7 series is illustrated in the following diagram. 
The support for the Thumb instructions in the Cortex-M23 and Cortex-M33 cores is shown in the following diagram, where the yellow parts indicate the new instructions added in ArmV8-M series:
Thus, the second leg of our ARM exploration journey concludes! Until next time!