Previously, we introduced “What Did Intel’s First CPU Look Like? Introduction to Intel’s 4-Bit CPU“, with a CPU configured like today’s desktop computers, other components like motherboards and memory are necessary to build a complete system. Of course, for the Intel 4004, these are also essential. Below, we will introduce the prototype of modern computers – the microcomputer MCS-4 (based on Intel 4004).
Old CPU Revelation –MicrocomputerMCS-4
Busicom 141-PF *Printing Calculator
The above isBusicom 141-PF *Printing Calculator (a microcomputer composed of a set of four chips, calledMCS-4. It includes a Central Processing Unit (CPU) chip – 4004, a Read-Only Memory (ROM) chip for custom applications, a Random Access Memory (RAM) chip for data processing, and a register chip for shift storage – Input/Output (I/O) ports.), after reverse engineering by foreign experts, the schematic diagram was obtained, as shown below:
Reverse-engineered calculator
MCS-4 can only minimally operate on4001 ROM and 4004 CPU (minimum system), but its design can run normally in RAM and shift registers. Additionally, the two chips 4008 and 4009 expanded the system, allowing it to work with any existing memory chip selection from Intel.
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Part
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Description
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4001
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Read-Only Memory
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4002
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Memory
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4003
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Shift Register
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4004
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Main Control Board
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4008
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Address Latch
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4009
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I/O Interface
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4001 is a 256×8 bit mask programmable ROM and 4-bit I/O port
4001 is a 2048-bit metal mask programmable ROM that provides custom microprogram display functionality for the MCS-4 microcomputer.
320-bit RAM and 4-bit output port
4002 performs two functions. As RAM, it stores 320 bits in 4 registers, each containing 24 four-bit characters (16 main memory characters and 4 status characters). As a medium for communication with peripheral devices, it has 4 output lines and corresponding control logic to perform outputs.
10-bit serial in/parallel out shift register (SR)
4003 is a 10-bit static shift register with serial input, parallel and serial output data, its function is to increase the number of output lines, interfacing with I/O devices such as keyboards, displays, printers, teletypes, switches, card readers, and A-D converters. WeChat: OpenFPGA
What Did Intel’s First CPU Look Like? Introduction to Intel’s 4-Bit CPU
Instruction Execution Cycle
The detailed functional specifications describe the operation of the system, instruction set, CPU activities for each instruction, and some programming and hardware examples. These detailed functional specifications are published separately and available upon request.
Below is a brief overview of the system operationMCS-4 uses a 10.8 usec instruction cycle. The CPU (4004) generates synchronization signals (SYNC) indicating the start of the instruction cycle and sends them to the ROM (4001) and RAM (4002). WeChat: OpenFPGA
Basic instruction execution requires 8 or 16 cycles of a 750 kHz clock. In a typical sequence, the CPU sends a 12-bit address to the ROM in the first three cycles (A1, A2, A3). The selected ROM chip sends an 8-bit instruction (OPR, OPA) to the CPU in the next two cycles (M1. M2), and then interprets and executes the instruction in the last three cycles (X1. X2. X3).
The CPU, RAM, and ROM can be controlled by an external reset line. When reset is activated, the contents of registers and flip-flops are cleared. After reset, the CPU will start from address 0 and CM-RAM0.
MCS-4 can have up to 4K x 8-bit ROM words, 1280 x 4-bit RAM, and 128 I/O lines without any connection logic. By adding some simple gates, MCS-4 can have up to 48 combinations of RAM and ROM and 192 I/O lines.
4001, 4002, and 4004 are connected by a 4-line data bus (D0, D1, D2, D3) for all information flow between chips, except for control signals sent by the CPU on an additional 6 lines. The interconnection of the MCS-4 system is shown in the above diagram, displaying an expanded configuration. The minimum system configuration consists of one CPU (4004) and one ROM (4001). The instruction cycle diagram shows the activity on the data bus during each clock cycle and how the basic instruction cycle is broken down. WeChat: OpenFPGA
Each data bus output buffer can have three possible states: “1″, “0”, and floating. At any given time, only one output buffer is allowed to drive the data line, so all other buffers must be in a floating state. However, multiple input buffers can receive data simultaneously on each data line. MCS-4 has a very powerful instruction set that allows for binary and decimal arithmetic. It includes conditional branching, jumps to subroutines, and provides effective use of ROM lookup tables through indirect addressing. Typically, two 8-bit numbers can be added in 850 usec.
From the above, the system interconnection diagram can be obtained
Reference Links:https://www.4004.com/busicom-replica.html
http://www.intel4004.com/
https://en.wikichip.org/wiki/intel/mcs-4
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