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Content Summary
This book first presents seven evaluation criteria for an instruction set, including cost, simplicity, performance, separation of architecture and implementation, room for improvement, code size, and ease of programming/compiling/linking. It introduces the elegant design of RISC-V and the numerous trade-offs involved from a holistic system perspective based on these seven criteria. Additionally, the book discusses the designs of x86, ARM, and MIPS, and quantitatively compares them through insertion sort and DAXPY (double-precision multiply-add) programs, highlighting the advantages of RISC-V and elaborating on the impact of instruction set design on computer systems. If you are a student, this book will be an excellent extracurricular reading that helps you establish a complete understanding of computer systems; if you are a teacher, this book will provide you with rich real-world examples that can inspire your teaching; if you are a professional in the relevant field, this book will not only broaden your horizons but also serve as a convenient reference manual to help you complete your work more easily.
Author Biography
David Patterson has served as a professor in the Department of Computer Science at the University of California, Berkeley for 40 years, retiring in 2016 and joining the Google Brain project as a distinguished engineer. He is also the vice-chair of the board of directors of the RISC-V Foundation and the director of the RISC-V International Open Source Lab.
He has been appointed chair of the Berkeley Computer Science Department and has been elected president of the Computing Research Association (CRA) and the Association for Computing Machinery (ACM).
In the 1980s, he led four generations of Reduced Instruction Set Computer (RISC) projects, and the new RISC from Berkeley was thus named “RISC Five” (the fifth generation of RISC). He and Andrew Waterman are among the four architects of RISC-V.
In addition to RISC, his most notable research project is the Redundant Arrays of Inexpensive Disks (RAID). Based on this research, he has published numerous papers, authored seven books, and received over 40 honors, including being elected to the National Academy of Engineering and the National Academy of Sciences, inducted into the Silicon Valley Engineering Hall of Fame, and receiving distinguished achievement awards from ACM, CRA, and SIGARCH. His teaching awards include the Distinguished Teaching Award (UC Berkeley), the Karlstrom Outstanding Educator Award (ACM), the Mulligan Educational Medal (IEEE), and two Textbook Excellence Awards (Text and Academic Authors Association).
His recent honors include the Tapia Achievement Award, the BBVA Foundation Frontiers of Knowledge Award, and the ACM Turing Award, the latter two of which he received jointly with John Hennessy. He earned all his degrees from UCLA, which also awarded him the Outstanding Engineering Alumni Award. He grew up in Southern California and enjoys body surfing, cycling, and playing soccer with his sons, as well as hiking with his wife. They fell in love in high school and celebrated their 55th wedding anniversary in 2022.
Andrew Waterman is the Chief Engineer and co-founder of SiFive, a company founded by the inventors of the RISC-V architecture to provide low-cost custom chips based on RISC-V. He earned his Ph.D. in Computer Science from UC Berkeley. During this time, he became frustrated with the unpredictability of existing instruction set architectures and participated in the design of the RISC-V ISA and the first RISC-V microprocessor. Andrew has made significant contributions to several open-source projects, including the open-source Rocket chip generator based on the RISC-V instruction set, the Chisel hardware construction language, and the RISC-V versions of the Linux operating system kernel, GNU C compiler, and C library. He also holds a master’s degree from UC Berkeley, where he conducted preliminary work on RISC-V compressed extensions, and a bachelor’s degree in engineering from Duke University.
Table of Contents
Chapter 1 Why RISC-V 1
1.1 Introduction 2
1.2 Modular ISA and Incremental ISA 3
1.3 Introduction to ISA Design 5
1.4 Overview of the Book 11
1.5 Conclusion 13
1.6 Further Reading 14
Chapter 2 RV32I: RISC-V Base Integer Instruction Set 16
2.1 Introduction 17
2.2 RV32I Instruction Format 18
2.3 RV32I Registers 21
2.4 RV32I Integer Computation 23
2.5 RV32I Load and Store 25
2.6 RV32I Conditional Branch 26
2.7 RV32I Unconditional Jump 27
2.8 Other RV32I Instructions 28
2.9 Comparison of RV32I, ARM-32, MIPS-32, and x86-32 through Insertion Sort 28
2.10 Conclusion 34
2.11 Further Reading 36
Chapter 3 RISC-V Assembly Language 37
3.1 Introduction 38
3.2 Calling Conventions 38
3.3 Assembler 41
3.4 Linker 46
3.5 Static and Dynamic Linking 49
3.6 Loader 49
3.7 Conclusion 50
3.8 Further Reading 50
Chapter 4 RV32M: Multiplication and Division Instructions 51
4.1 Introduction 52
4.2 Conclusion 54
4.3 Further Reading 55
Chapter 5 RV32F and RV32D: Single and Double Precision Floating Point 56
5.1 Introduction 57
5.2 Floating Point Registers 60
5.3 Floating Point Load, Store, and Arithmetic Operations 62
5.4 Floating Point Conversion and Data Transfer 63
5.5 Other Floating Point Instructions 63
5.6 Comparison of RV32FD, ARM-32, MIPS-32, and x86-32 through DAXPY Program 65
5.7 Conclusion 68
5.8 Further Reading 68
Chapter 6 RV32A: Atomic Instructions 70
6.1 Introduction 71
6.2 Conclusion 73
6.3 Further Reading 74
Chapter 7 RV32C: Compressed Instructions 75
7.1 Introduction 76
7.2 Comparison of RV32GC, Thumb-2, microMIPS, and x86-32 81
7.3 Conclusion 82
7.4 Further Reading 82
Chapter 8 RV32V: Vectors 83
8.1 Introduction 84
8.2 Vector Computation Instructions 85
8.3 Vector Registers and Dynamic Types 86
8.4 Vector Load and Store 88
8.5 Parallelism of Vector Operations 89
8.6 Conditional Execution of Vector Operations 90
8.7 Other Vector Instructions 90
8.8 Example: Writing DAXPY Program with RV32V 92
8.9 Comparison of RV32V, MIPS-32 MSA SIMD, and x86-32 AVX SIMD 93
8.10 Conclusion 97
8.11 Further Reading 99
Chapter 9 RV64: 64-bit Address Instructions 100
9.1 Introduction 101
9.2 Comparison of RV64 with Other 64-bit ISAs through Insertion Sort 105
9.3 Program Size 112
9.4 Conclusion 113
9.5 Further Reading 114
Chapter 10 RV32/64 Privileged Architecture 115
10.1 Introduction 116
10.2 Machine Mode for Simple Embedded Systems 117
10.3 Exception Handling in Machine Mode 119
10.4 User Mode and Process Isolation in Embedded Systems 124
10.5 Supervisor Mode in Modern Operating Systems 126
10.6 Paging Virtual Memory 128
10.7 Identification and Performance CSR 133
10.8 Conclusion 136
10.9 Further Reading 136
Chapter 11 Future RISC-V Optional Extensions 137
11.1 “B” Standard Extension: Bit Manipulation 138
11.2 “E” Standard Extension: Embedded 138
11.3 “H” Privileged Architecture Extension: Support for Hypervisors 138
11.4 “J” Standard Extension: Dynamic Translation Languages 138
11.5 “L” Standard Extension: Decimal Floating Point 139
11.6 “N” Standard Extension: User Mode Interrupts 139
11.7 “P” Standard Extension: Compressed SIMD Instructions 139
11.8 “Q” Standard Extension: Quad Precision Floating Point 140
11.9 Conclusion 140
Appendix A RISC-V Instruction List 141
Appendix B Translating RISC-V to Other ISAs 187