The Application of AI in Chip Verification: ChipAgents is Reshaping Chip Validation

Do not worry about the tedious tasks,

Do not lament the long nights of debugging.

Introduction:

Hello to all the verification friends working on the front lines! What do we fear the most in our field?

When the specifications change, the RTL and verification environment must be rebuilt from scratch;
After running regression all night, you come in the morning to see a line of “Error”;
The most painful part—Debugging! A strange failure, checking waveforms, flipping logs, debugging from afternoon tea to the next afternoon tea…

The Moore’s Law for chip scale is nearing its end, but the “new Moore’s Law” for chip complexity has just begun. 70% of chip development costs are in verification, and we verification engineers are fighting against exponentially increasing complexity with our “flesh and blood.” But what if debugging could be taken over by AI? What if the UVM environment could be generated with a single command?

Today, we will delve into a new platform that has recently stirred up a storm in the EDA community—ChipAgents. Is it just a grand vision, or can it really rescue us from “Debug Hell”?

What is ChipAgents? How is it different from “ordinary AI”?

First, it is important to clarify that ChipAgents is not a single tool; it is anAI-native EDA platform, launched by a company called Alpha Design AI.

The core concept is called “Agentic AI”, which means “agent AI.”

What does this mean?

Ordinary AI: You give it a task, and it gives you an answer. Like a “Swiss Army knife,” it has many functions but may not be precise.
ChipAgents’ “Agentic AI”: This is more like an “AI expert team.”

There is an “RTL Design Agent” (RTL Agent);
There is a “UVM Verification Agent” (UVM Agent);
There is a “Debug Agent” for waveform debugging;
And a “Manager Agent” to coordinate them.

When you give a complex task, such as “verify this module based on this Spec,” the Manager Agent will break down the task:

“RTL Agent, please analyze the RTL code and extract key interfaces and functionalities.”
“UVM Agent, based on the RTL Agent’s analysis, set up a UVM test platform.”
“UVM Agent, write a few basic test cases to run.”
“Debug Agent, keep an eye on it; if it fails, analyze the logs and waveforms immediately to find out which line of RTL code has the bug.”

ChipAgents aims to build a self-coordinating AI team to simulate (or even replace) our human engineers’ design and verification processes.

Core Applications: The “Magic” of ChipAgents in the Full Design-Verification Process

This is the part we care about the most. As verification engineers, what can this tool actually help us with?

1. From “Human Language” to RTL: AI-Assisted Design

The root of all evil in our verification is RTL. The quality of RTL determines the difficulty of our debugging.

Traditional Process:

The design engineer looks at the Spec document (Word/PDF).
The engineer (human) interprets the Spec and then manually writes Verilog/VHDL.
This “translation” process is prone to errors, leading to RTL being born with bugs.

ChipAgents’ Process:

You feed it a Spec written in natural language (for example, “design a 4×4 Round-Robin arbiter”).
The “RTL Agent” will automatically generate a draft of RTL code.
It can even analyze and optimize existing RTL code, such as checking for timing risks, power issues, or logical redundancies.

Significance for Verification: It reduces a lot of fundamental bugs caused by misinterpretation of the Spec right from the “source.”

2. Say Goodbye to “CV Engineers”: Automated UVM Environment Setup

This is ChipAgents’ first major advantage for us verification engineers.

Traditional Process:

Upon receiving RTL, first check the interfaces (AXI, APB, or custom?).
Start “setting up the environment.” Copy and paste (Ctrl+C, Ctrl+V) an old project’s UVM framework.
Manually write Interface, Config, Driver, Monitor, Scoreboard…
This process is tedious, cumbersome, and time-consuming; we jokingly refer to ourselves as “UVM template CV engineers.”

ChipAgents’ Process:

The “UVM Agent” automatically reads the RTL code (or design Spec).
It can automatically identify interfaces and bus protocols.
One-click generation of a complete UVM test platform (Testbench) architecture, including all components (Agent, Sequencer, Driver, Monitor, Scoreboard) and their connections.
It can also generate basic sequences and test cases (such as register read/write tests).

Significance for Verification: It liberates us from tedious “template code.” We no longer need to worry about “how to set up the environment” but can focus 100% on “verification strategy”—what should I test? Which scenarios are most likely to have bugs?

3. The “Holy Grail” of Verification: AI Waveform Debugging and Bug Localization

This is ChipAgents’ most “frightening” weapon, and the “ultimate blessing” for us verification engineers.

Imagine your most painful debugging experience:

Traditional Process:

“Hmm, why is thisvalid signal low?”
“Trace its driving signalA.”
“A is controlled byB andC<code>.
“B comes from FSM, let me check the state machine… oh, the state jumped incorrectly.”
“Why did the FSM jump incorrectly? Check its inputs… (3 hours later)…”

Test case failed, and the log reported a scoreboard mismatch.
You open the waveform (Verdi/DVE/Simvision) and find the error point.
Start “manually” backtracking:
In the end, you find that 5000 cycles ago, a state transition condition in the RTL was incorrectly written with a&.
You (exhausted) report a bug to the design engineer.

ChipAgents’ Process:

Test case failed.
You (or even without you) activate the “Debug Agent.”
The AI Agent simultaneously reads the log file and waveform file (VCD/FSDB)..
It understands the UVM error message (“Scoreboard Mismatch”).
It autonomously executes our previous “manual backtracking” logic in the waveform, but at a speed 1000 times faster than ours.
Finally, it gives you a report:

“In the RTL file fsm_ctrl.v at line 88, the state machine CURRENT_STATE received the req_valid signal while in the IDLE state, but due to the arb_grant signal being low, it incorrectly transitioned to the WAIT state instead of the expected BUSY state. This caused the data_valid signal to fail to rise after 3 clock cycles, ultimately triggering a Scoreboard Mismatch at 5024 ns.”
(Furthermore) it can even suggest RTL fix code.

Significance for Verification: This is not just “assistance”; it is nearly “fully automated.” It promises to reduce our most time-consuming debugging work (which accounts for over 50% of verification time) from “days” to “minutes”.

4. Intelligent Coverage Closure

Coverage is the mark of our verification “completion.”

Traditional Process:

Run regression, check the coverage report, and find functional coverage at 90%, code coverage at 95%.
The remaining 10% is “hard-core” and difficult to hit.
The verification engineer (human) analyzes which “nooks and crannies” have not been run, then manually writes directed test cases or modifies the constraints of random strategies.

ChipAgents’ Process:

The AI Agent analyzes the coverage report and existing test cases.
It can understand which functionalities have not been covered.
It automatically generates new, highly directed test cases or constraints specifically to “attack” these uncovered points.

Significance for Verification: It greatly accelerates the final “sprint” phase of “coverage closure.”

What Does This Mean for Us (Verification Engineers)?

At this point, some friends may ask: “Is it so powerful? Are we going to be unemployed?”

On the contrary.

AI EDA tools, especially platforms like ChipAgents, are not meant to “replace” engineers but to “enhance” them. It changes the nature of our work:

From “manual labor” to “intellectual labor”:

AI will take over all “repetitive” and “process-oriented” tasks, such as setting up environments, writing template code, and manual debugging.
We will be liberated to think about higher-level, more valuable issues.

Evolution of the Verification Engineer Role:

“UVM Code Farmer” (decrease) -> “AI Tuner” (increase): Our job becomes “guiding” AI to verify and checking the results of AI’s work.
“Debug Expert” (remains the same, but the method changes) -> “Verification Strategy Architect” (increase): Our core value is no longer “how quickly to find bugs,” but “how to design a seamless verification plan (vPlan)” to ensure that AI (and ourselves) can cover all possible risks.

Our New “Three Axes”:

Define the Problem: Accurately describe to AI what you want to verify (write a good Spec).
Develop Strategy: Design the verification architecture and define the coverage model.
Review Results: Review the code generated by AI and the bugs located, and do the final sign-off.

Conclusion: Embrace, Not Fear

The emergence of ChipAgents is akin to the transition from “hand-drawn schematics” to “Verilog,” from “handwritten testbenches” to “UVM”—it is a generational revolution in tools.

It will not make excellent verification engineers unemployed, but it will eliminate those “screwdriver” engineers who “only know how to set up environments, do not want to debug, and do not think about strategies”..

For those of us at the forefront of technology, this is not a crisis, but rather a tremendous opportunity. It means we can finally escape the endless “manual labor” and truly engage in the “core verification work” that defines the success or failure of chips.

Friends, the wave of AI has already reached the shores of EDA. Our choice is to build high walls or learn to surf?

Alright, that’s all for today about ChipAgents. What are your thoughts on this platform? Do you think AI debugging is really reliable? What part of the verification work do you most hope AI will help you with? Feel free to leave your comments for discussion!

*Disclaimer: This article is original by the author. The content reflects the author’s personal views, and the reposting by Luko Verification is only to convey a different perspective, not representing Luko Verification’s endorsement or support of this view. If there are any objections, please contact Luko Verification.