This article is reprinted from the Jishu Community
Jishu Column: Lingdong MM32 MCU
The Cortex-M0 System Control Block (SCB) is one of the main modules of the core peripherals, providing system control and execution information, including configuration, control, and reporting system exceptions.
To improve software efficiency, CMSIS simplifies the representation of SCB registers. In CMSIS, the system control register structure is as follows:
typedef struct
{ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset:0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U];/*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
1. CPUID
The CPUID base address register contains information related to the processor model and version. It is read-only and can be accessed through application software, debuggers, and programmers to obtain the type and version information of the processor.
Address: 0xE000ED00
Reset value: 0x410CC200
In this context, CPUID is different from the 96-bit UID of the MCU that we often mention. CPUID is the processor ID number provided and implemented by Arm, which allows us to know kernel models and versions. The 96-bit UID is the MCU product ID, belonging to MM32, provided by Shanghai Lingdong Microelectronics Co., Ltd., and implemented according to certain rules. The unique identity provided by the 96-bit product ID is unique for any series of microcontrollers under any circumstances. Users cannot modify this identity under any circumstances.
The MCU also has a DEV_ID code, which defines the device number and silicon version number of the MCU. It is part of the DBG_MCU and is mapped to the external APB bus. This code can be accessed through the SW debug interface (2 pins) or through user code.
DEV_ID Address: 0x40013400, supports only 32-bit access and is read-only.
In the CMSIS driver library, you can directly use “SCB->CPUID” to obtain the processor ID. Reading the CPUID, UID, and DEV_ID of MM32F0130 is shown below:
CPUID (0x410CC200) parses processor information:
2. ICSR (Interrupt Control and State Register)
-
The exception number of the currently processed exception
-
Whether there are preempted active exceptions
-
The exception number of the highest priority pending exception
-
Whether there are any interrupts pending
Address: 0xE000ED04
Reset value: 0x0000 0000
Some control bits in ICSR are for debugging purposes only. In most cases, applications will only use ICSR to control or check the system exception pending status.
PendSV (Pendable Service Call) exception is very important for OS operations, and its priority can be set programmatically. You can trigger PendSV interrupt by setting bit 28 of the Interrupt Control and State Register ICSR to 1. Unlike SVC exceptions, it is imprecise, so its pending state can be set within higher priority exception handling and executed after the higher priority handling is completed. Utilizing this feature, if PendSV is set to the lowest exception priority, it allows PendSV exception handling to be executed after all other interrupt handling is completed, which is very useful for context switching and is key in various OS designs. In typical systems with embedded OS, processing time is divided into multiple time slices.
To start PendSV interrupt, write 1 to bit 28 of the Interrupt Control and State Register ICSR. If the interrupt is enabled and a PendSV exception service function is written, the kernel will respond to the PendSV exception and execute the PendSV exception service function, allowing task switching to be performed in the PendSV interrupt service function.
3. AIRCR (Application Interrupt and Reset Control Register)
AIRCR provides byte order status for data access and system reset control.
To write to this register, you must write the 0x05FA VECTKEY field; otherwise, the processor will ignore the write.
Address: 0xE000ED0C
Reset value: 0xFA05 0000
Any write operation to this register must write 0x05FA to AIRCR[30:16]; otherwise, the write operation will be invalid. If a half-word read is needed, you must write 0xFA05.
The system execution soft reset function in the application:
__STATIC_INLINE void NVIC_SystemReset(void)
{ __DSB(); // Ensure all uncompleted memory accesses including buffered writes are completed before reset
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); // Ensure memory access is completed
for(;;) /* wait until reset */
{
__NOP();
}
}
4. SCR (System Control Register)
The SCR controls the characteristics of entering and exiting low-power states.
Address: 0xE000ED10
Reset value: 0x0000 0000
The SCR (System Control) register can choose to use immediate sleep or sleep on exit. When the SLEEPONEXIT bit of the SCR register is 0, immediate sleep is used; when it is 1, sleep on exit is used.
The function to enter stop mode for MM32F0130:
void PWR_EnterSTOPMode(u32 regulator, u8 stop_entry)
{ PWR->CR |= regulator;
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
(stop_entry == PWR_STOPEntry_WFI) ? __WFI() : __WFE();
}
5. CCR (Configuration and Control Register)
CCR is a read-only register that indicates certain aspects of the behavior of the Cortex-M0 processor.
Address: 0xE000ED14
Reset value: 0x0000 0204
SCB->CCR register controls whether division by zero and unaligned memory accesses trigger a HardFault.
6. SHPR (System Handler Priority Registers)
Since SHPR1 only exists in the ARMv7-M architecture, Cortex-M0 only uses SHPR2 and SHPR3 for system priority registers, and does not have SHPR1.
SHPR2-SHPR3 registers set the priority level of exception handlers with configurable priorities, from 0 to 192.
SHPR2-SHPR3 are word-accessible.
To access system exception priorities using CMSIS, you can use the CMSIS functions:
uint32_t NVIC_GetPriority(IRQn_Type IRQn)
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
The system fault handler, as well as the priority field and register for each handler are:
6.1 SHPR2 (System Handler Priority Register 2)
Address: 0xE000ED1C
Reset value: 0x0000 0000
6.2 SHPR3 (System Handler Priority Register 3)
If your device does not implement the SysTick timer, this field is reserved.
Address: 0xE000 ED20
Reset value: 0x0000 0000
SVC, PendSV, and SysTick programmable interrupts are often used in software development above the operating system. SVC is used to generate requests for system function calls. For example, the operating system does not allow user programs to directly access hardware, but provides some system service functions. User programs use SVC to issue calls to system service functions to indirectly access hardware. Therefore, when a user program wants to control specific hardware, it generates an SVC exception, and the SVC exception service routine provided by the operating system is executed, which then calls the relevant operating system function to complete the service requested by the user program.
Another related exception is PendSV, which works in conjunction with SVC. On one hand, SVC exceptions must be responded to immediately (if they cannot be responded to immediately due to priority not being higher than the currently processed exception or other reasons, it will lead to a HardFault). When the application executes SVC, it expects the requested response to be immediate. On the other hand, PendSV can be suspended like a normal interrupt (unlike SVC which will lead to a HardFault). The OS can use it to “defer execution” of an exception until other important tasks are completed. The method to suspend PendSV is to write 1 to the PendSV pending register in the NVIC. After being suspended, if the priority is not high enough, it will be deferred. A typical use case for PendSV is during context switching (switching between different tasks). There are two ready tasks, and the context switch can be triggered in the following situations:
Executing a system call or a SysTick interrupt (needed in round-robin scheduling)
Both ARMv7-M and ARMv6-M have the same SCB register names, but the number of registers and effective control bits in ARMv7-M is much richer than in ARMv6-M. Generally speaking, ARMv6-M is upward compatible with ARMv7-M, which means that software developed for ARMv6-M does not need modification to run on ARMv7-M. This is also the reason why Arm can quickly switch from one platform to another. For further research, you can refer to the “ARMv6-M Architecture Reference Manual” white paper.
Recommended Reading
Technical Sharing | Cortex-M0 Interrupt Control and System Control (Part Three)
Technical Sharing | Cortex-M0 Interrupt Control and System Control (Part Two)
Technical Sharing | Cortex-M0 Interrupt Control and System Control (Part One)
Copyright belongs to the original author. If there is any infringement, please contact for deletion.
END
About Anxin Education
Anxin Education is an innovative education platform focused on AIoT (Artificial Intelligence + Internet of Things), providing a comprehensive AIoT education solution from primary and secondary schools to higher education institutions.
Anxin Education relies on Arm technology to develop ASC (Arm Smart Connectivity) courses and talent training systems, which have been widely applied in higher education industry-university-research cooperation and primary and secondary school STEM education, committed to cultivating talents in the field of intelligent connectivity that meet the needs of the times.
