Summary of Common Communication Interfaces in Embedded Development

In embedded systems, on-board communication interfaces refer to the communication paths or buses used to connect various integrated circuits with other peripheral devices. The following content summarizes commonly used on-board communication interfaces: including I2C, SPI, UART, and 1-Wire:

I2C Bus

The I2C bus is a  synchronous, bidirectional, half-duplex two-wire serial interface bus. Here, half-duplex means that at any given time, communication can only occur in one direction.

The I2C bus was developed and released by Philips Semiconductor in the 1980s. The initial design goal of I2C was to provide a simple method for connecting microprocessor/microcontroller systems to peripheral chips of televisions.

The I2C bus consists of two lines: the serial clock line SCL and the serial data line SDA.

The SCL line is responsible for generating the synchronous clock pulses.

The SDA line is responsible for transmitting serial data between devices.

The I2C bus is a shared bus system, allowing multiple I2C devices to be connected to it. Devices connected to the I2C bus can function as either master or slave devices.

The master device controls communication by initializing/terminating data transmission, sending data, and generating the required synchronous clock pulses.

The slave device waits for commands from the master device and responds to command reception. Both the master and slave devices can act as sending or receiving devices. Regardless of whether the master device is sending or receiving, the synchronous clock signal can only be generated by the master device.

On the same bus, I2C supports the simultaneous presence of multiple master devices. Figure 1-1 shows the connection relationship between master and slave devices on the I2C bus.

Summary of Common Communication Interfaces in Embedded Development

When the bus is idle, both SDA and SCL are in a high state. When the master wants to communicate with a slave, it first sends a start condition, then sends the slave address and read/write control bit, and then transmits data (either sending or receiving). At the end of data transmission, the master sends a stop condition. Each byte transmitted consists of 8 bits, with the high bit first and the low bit last.

Start Condition: When SCL is high, the master pulls SDA low, indicating that data transmission is about to begin.
Slave Address: The first byte sent by the master is the slave address, with the highest 7 bits being the address and the lowest bit being the R/W read-write control bit, where 1 indicates a read operation and 0 indicates a write operation.

Generally, slave addresses can be in 7-bit address mode and 10-bit address mode. In the case of 10-bit address mode, the first byte’s top 7 bits are a combination of 11110XX, where the last two bits (XX) are the two highest bits of the 10-bit address, and the second byte contains the remaining 8 bits of the 10-bit slave address, as shown in the figure below:

Summary of Common Communication Interfaces in Embedded Development

Acknowledge Signal: After transmitting one byte of data, the receiver needs to reply with an ACK (acknowledge). When writing data, the slave sends ACK; when reading data, the master sends ACK. When the master reads the last byte of data, it can send NACK (Not acknowledge) followed by a stop condition.
Data: After sending the slave address, commands may be sent based on the slave, followed by data transmission, which can be sent by either the master or the slave, with each data byte being 8 bits, and there is no limit to the number of data bytes.
Repeated Start Condition: During a communication session, if the master needs to transmit data to different slaves or switch read/write operations, it can send another start condition.
Stop Condition: When SDA is low, the master pulls SCL high and keeps it high, then pulls SDA high, indicating that the transmission is over.

SPI Bus

The SPI bus is a  synchronous, bidirectional, full-duplex four-wire serial interface bus, originally proposed by Motorola. SPI consists of a system of “one master device + multiple slave devices.” It should be noted that as long as only one master device is activated at any time, multiple SPI master devices can exist in the system. It is commonly used for communication between EEPROM, FLASH, real-time clocks, AD converters, digital signal processors, and digital signal decoders.

To achieve communication, SPI has a total of four signal lines, which are:

Summary of Common Communication Interfaces in Embedded Development

(1) Master Out Slave In (MOSI): The signal line for transmitting data from the master device to the slave device, also known as Slave Input (SI/SDI).

(2) Master In Slave Out (MISO): The signal line for transmitting data from the slave device to the master device, also known as Slave Output (SO/SDO).

(3) Serial Clock (SCLK): The signal line for transmitting clock signals.

(4) Slave Select (SS): The signal line used to select the slave device, active low.

How to Use SPI:

Summary of Common Communication Interfaces in Embedded Development

The chip shown in the figure has two SPI controllers, corresponding to the SPI master device. Each SPI controller can connect multiple slave devices. Slave devices mounted on the same SPI controller share three signal pins: SCK, MISO, and MOSI, but each slave device’s CS pin is independent.

The master device selects the slave device by controlling the CS pin, which is generally active low. At any time, only one CS pin on an SPI master device can be active, allowing the connected slave device to communicate with the master device.

Therefore, the SPI communication method can use a “one master, multiple slaves” structure for communication. Each device connected to the bus has a unique address, the master device initiates data transmission and generates clock signals, and only one master device is allowed at the same time.

The slave device’s clock is provided by the master device through SCLK, while MOSI and MISO complete data transmission based on this pulse. The working timing mode of SPI is determined by the phase relationship between CPOL (Clock Polarity) and CPHA (Clock Phase). CPOL indicates the initial level state of the clock signal, where CPOL=0 means the clock signal starts low, and CPOL=1 means it starts high. CPHA indicates on which clock edge the data is sampled: CPHA=0 means sampling occurs on the first clock edge, while CPHA=1 means sampling occurs on the second clock edge.

Based on different combinations of CPOL and CPHA, there are four working timing modes: CPOL=0, CPHA=0; CPOL=0, CPHA=1; CPOL=1, CPHA=0; CPOL=1, CPHA=1.

UART

UART— Universal Asynchronous Receiver-Transmitter, is an asynchronous serial communication protocol that transmits each character of data one bit at a time. It is a frequently used data bus in application development.

Data transmission based on UART is asynchronous serial data transmission. UART serial data transmission does not require clock signals to synchronize the sending and receiving ends but relies on predefined configurations between the sending and receiving devices.

For both sending and receiving devices, their serial communication configurations (baud rate, unit word bit count, parity, start and stop bits, flow control) must be identical. By inserting specific bit sequences into the data stream, the start and end of communication can be indicated. When sending a byte of data, a start bit is added at the beginning of the bit stream, and a stop bit is added at the end. The least significant bit of the data byte follows immediately after the start bit.

The UART serial port is characterized by transmitting data one bit at a time, allowing for bidirectional communication with just two transmission lines, where one line sends data while the other receives data.

There are several important parameters for UART serial communication, including baud rate, start bit, data bits, stop bits, and parity bit. For two ports communicating via UART, these parameters must match; otherwise, communication will fail.

Summary of Common Communication Interfaces in Embedded Development

Start Bit: Indicates the beginning of data transmission, with a logic level of “0”.
Data Bits: Possible values are 5, 6, 7, 8, or 9, indicating the number of bits of data being transmitted. The typical value is 8, as one ASCII character is 8 bits.
Parity Bit: Used by the receiver to check the received data, ensuring the number of “1” bits is even (even parity) or odd (odd parity), thus verifying the correctness of data transmission. This bit is optional.
Stop Bit: Indicates the end of a data frame, with a logic level of “1”.
Baud Rate: The rate of serial communication, represented by the number of valid bits transmitted per unit time, measured in bits per second (bps). Common baud rate values include 4800, 9600, 14400, 38400, and 115200, with higher values indicating faster data transmission. A baud rate of 115200 means 115200 bits of data are transmitted per second.

1-Wire Interface

The 1-Wire interface is an  asynchronous half-duplex communication protocol developed by Maxim Dallas Semiconductor, also known as the Dallas 1-Wire® protocol. It utilizes a single signal line DQ for communication according to the master-slave communication model.

An important feature of the 1-Wire bus is that it allows energy to be transmitted over the signal line. The 1-Wire interface supports connecting a single master device and one or more slave devices on the bus.

Summary of Common Communication Interfaces in Embedded Development

Parallel Interface

The on-board parallel interface is typically used for communication between the system and peripheral devices, where peripheral devices are memory-mapped to the main control end of the system. As long as the embedded system’s main processor/controller has a parallel bus, devices that support the parallel bus can be directly connected to this bus system. Peripheral devices have control signal interfaces with the main control end, which can control data communication on the parallel bus. The control signals for communication include read/write signals and device select signals. Generally, peripheral devices have device select lines; only when the main control processor activates this line is the device valid.

The direction of data transmission can be from the main control end to the peripheral device or from the peripheral device to the main control end; this is controlled through read and write control signal lines. Only the main control processor can control the read control signal and write control signal. Generally, peripheral devices are memory-mapped to the main control processor, allowing access to the allocated address range. At this point, the device needs to use address decoding circuits to generate chip select signals.

When the address selected by the processor is within the device’s specified range, the decoding circuit triggers the chip select line, activating the device. The processor can then enable the corresponding control lines (RD\ and WD\) to read data from the device or write data to the device.

To achieve parallel communication, the system must strictly follow timing specifications. As mentioned earlier, parallel communication is initiated by the main control processor. If a peripheral device wants to initialize communication, it can send an interrupt to the processor to provide relevant information. To achieve this functionality, the device’s interrupt line must be connected to the processor’s interrupt line, and the main control processor must trigger the corresponding interrupt. It should be noted that the width of the data bus of the main control processor determines the width of the parallel interface, which can be 4, 8, 16, 32, or 64 bits, etc. The supported bus width of the device should be identical to that of the main control processor.

Summary of Common Communication Interfaces in Embedded Development

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Summary of Common Communication Interfaces in Embedded Development

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I2C Bus

SPI Bus

UART

1-Wire Interface

Parallel Interface

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