RISC-V: The Key to the Rise of Domestic Chips

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Introduction:

In the context of the rapid evolution of the semiconductor industry, the Instruction Set Architecture (ISA) has become the core hub of chip design. Traditional closed-source architectures such as ARM and x86 have long dominated the market, but with the rising demand for chip customization, power efficiency, and security control in emerging fields like the Internet of Things, artificial intelligence, and automotive electronics, “open-source” and “customizable” have become the key to new tracks.

As the first truly open-source instruction set architecture, RISC-V has quickly sparked discussions in both industry and academia due to its zero licensing fees, modular design, and high scalability, and is moving towards application deployment from laboratory to mass production.

Today, let’s explore RISC-V and uncover why it will become the key to the rise of our domestic chips.

Reasons and Advantages for the Recent Popularity of RISC-V Instruction Set

Friends who follow AISC may have noticed that more and more semiconductor companies are launching RISC-V architectures.For example, Western Digital announced in 2018 the open-sourcing of its SweRV Core™ processor core to accelerate the development of customized architectures from edge to core;Alibaba’s Pingtouge launched its first multi-core 64-bit XuanTie 910 processor in 2019, targeting high-performance scenarios such as AI, 5G, IoT, and autonomous driving;Recently, Pingtouge also released the C930 high-performance RISC-V chip for server-level applications in 2025.Behind this wave of significant deployment and mass production news, RISC-V has quickly gained industry attention due to its multiple technical and commercial advantages:

1. Zero Licensing Fees and Open Licensing RISC-V follows the BSD-style open-source protocol, does not charge any licensing fees, and any enterprise or individual can use, modify, and redistribute it for free, effectively reducing initial costs and legal compliance barriers..

2. Modular and Customizable Instruction Set From the basic RV32I/RV64I to standard extensions such as M (multiplication and division), A (atomic), F/D (floating-point), C (compressed), and V (vector), as well as fully customized private instructions, designers can flexibly pull or remove features based on performance, power consumption, and area requirements, avoiding unnecessary resource waste..

3. Highly Customizable Private Extensions Manufacturers can define dedicated instructions for AI acceleration, cryptographic computing, or signal processing beyond the standard ISA, significantly enhancing the execution efficiency and security of specific algorithms at the hardware level..

4. Rich and Growing Open-Source Ecosystem Mainstream compilers (GCC, LLVM), simulators (Spike, QEMU), and debuggers (GDB) fully support RISC-V; operating systems such as Linux, Zephyr, FreeRTOS, and various middleware are rapidly adapting, forming a complete industrial ecosystem from IP to software toolchain..

5. Diverse Supply Chain and Security Control In the context of increasing geopolitical and industrial chain risks, RISC-V provides governments and enterprises with the possibility to break free from dependence on a single ISA vendor, especially in the Chinese market, where “self-control” has become one of the driving forces..

It is these technical and commercial advantages that have led large storage manufacturers, internet giants, and new IP providers to compete in launching RISC-V-based solutions, collectively pushing this open-source instruction set architecture towards a broader application stage.

Instruction Set Comparison

Since many of our fans do not come from a CPU/GPU background, it is necessary to provide a detailed explanation of the instruction set:

What is an “Instruction Set”? Imagine a processor as a worker in a factory workshop, and the “instructions” are the operational commands given to the worker. For example, “move the goods from here to there,” “add two numbers,” or “check if this part is qualified.” Different instruction sets are a complete set of commands that the worker can understand.

• Some instructions are basic, like “add,” “subtract,” “pick up goods,” “put down goods”;

• Some instructions are more advanced, like “quickly sort a batch of goods” or “bulk encrypt”;

• “Extensions” are like equipping the worker with new tools, allowing them to complete more advanced tasks;

• “Compressed instructions” are like telling them the same action in shorter words, saving communication time and warehouse space.

It can be said that the instruction set is the interface between software and hardware; simply put, the instruction set is the “translator” that facilitates communication between software and hardware, and is an indispensable foundational part of the chip industry.

Using different instruction sets represents different CPUs. Currently, CPUs on the market are mainly classified into two camps: one is the complex instruction set (CISC) CPUs led by Intel and AMD, and the other is the reduced instruction set (RISC) CPUs led by IBM, ARM, and RISC-V.

Different instruction sets determine how CPUs process information. From the perspective of instruction sets, CPU efficiency can be improved in two ways: either by reducing the number of instructions required for each program or by reducing the number of clock cycles required for each instruction.

CISC focuses more on the former, while RISC emphasizes the latter. Currently, CISC instruction sets are relatively complex, providing a rich set of instructions that can reduce the programming workload for developers.

However, with the development of computer science, it has been found that this complexity can lead to a decline in processor performance and energy efficiency. Therefore, RISC emerged, adopting a simpler and more efficient design philosophy, optimizing the instruction set to improve processor performance and energy efficiency, becoming the absolute mainstream in all emerging fields since the 21st century.

Currently, instruction sets can generally be divided into the following categories:

Introduction to RISC-V Architecture

The RISC-V instruction set architecture (ISA) consists of the following aspects:

• Base Integer Instruction Set (Base Integer ISA): This is the core part that RISC-V processors must implement.

• RV32I: 32-bit base integer instruction set, containing about 40 instructions, operating on 32 32-bit integer registers (x0-x31, where x0 is always 0).

• RV64I: 64-bit base integer instruction set, operating on 32 64-bit integer registers.

• RV128I: 128-bit base integer instruction set (currently still under development and standardization).

• There is also an embedded version RV32E, which has only 16 integer registers and is suitable for resource-constrained microcontrollers.

• Standard Extensions: These are optional, standardized instruction set extensions represented by a single letter. Some common standard extensions include:

• M: Integer multiplication and division instructions.

• A: Atomic operation instructions for multi-core synchronization.

• F: Single-precision floating-point instructions.

• D: Double-precision floating-point instructions.

• Q: Quad-precision floating-point instructions.

• C: Compressed instruction extension. Allows common 32-bit instructions to be compressed into 16-bit instructions, thereby reducing code density and improving cache efficiency, especially suitable for memory-constrained embedded systems.

• B: Bit manipulation extension.

• V: Vector processing extension for high-performance computing and data parallel processing.

• P: Packed SIMD (Single Instruction Multiple Data) extension.

• H: Hypervisor extension for supporting virtualization.

• More extensions for specific functions are continuously being developed and standardized.

A typical RISC-V processor name reflects the instruction sets it supports, for example, RV64IMAFDC indicates that the processor supports the 64-bit base integer instruction set, integer multiplication and division, atomic operations, single-precision floating-point, double-precision floating-point, and compressed instructions.

• Privileged Architecture: RISC-V defines different privilege levels to support operating systems and system security. The main levels include:

• User Mode (U-mode): The mode in which user applications run.

• Supervisor Mode (S-mode): The mode in which the operating system kernel runs.

• Machine Mode (M-mode): The highest privilege level, usually used for bootloaders and low-level firmware. This is the mode that all RISC-V hardware platforms must implement.

• Hypervisor Mode (H-mode): Used to support virtual machine monitors (VMM) or hypervisors.

• Instruction Encoding Formats: All standard instructions are based on 32-bit alignment, with six main formats:

• Diversity of Microarchitecture Implementations: Despite the consistency of the ISA, specific microarchitecture designs can be highly customized.

• Classic Five-Stage Pipeline: IF → ID → EX → MEM → WB, suitable for entry-level and mid-range cores.

• Superscalar + Out-of-Order: Register renaming, out-of-order issue/commit, improving IPC, aimed at high-performance cores.

• Deep Pipelining and Branch Prediction: Combining dynamic prediction and speculative execution, used for server-grade processors.

• Single-Cycle or Two-Stage Pipeline: Extremely simplified design, suitable for ultra-low latency MCUs and hard real-time applications.

Applications and Development Trends of RISC-V

Due to the characteristics of different instruction sets, both the reduced instruction set RISC-V and ARM have good low-power characteristics, making them suitable for embedded systems, IoT devices, and mobile devices in low-energy scenarios. In contrast, x86 is relatively high-power, suitable for high-performance computing, cloud computing, and big data analysis in high-energy scenarios.

• Embedded and IoT

• Espressif, SiFive, and Alibaba Pingtouge have launched multiple low-power MCUs, widely used in smart homes, wearables, and industrial sensors.

• Automotive Electronics and ADAS

• RISC-V is beginning to explore fields such as BMS, IVI, and domain controllers; safety extensions and functional safety certification (ISO 26262/ASIL) are key to advancement.

• AI and High-Performance Computing

• Vector extension V + private custom instructions are becoming popular for AI accelerators; RISC-V-based open-source accelerator boards and custom SoCs are being released one after another.

• Data Centers and Servers

• Although still in the testing and validation stage, some cloud vendors and the open-source community have initiated RISC-V server processor projects, aiming for better energy efficiency and cost-effectiveness.

• Ecology and Standardization

• RISC-V International regularly publishes standard specifications; projects like the Linux kernel, LLVM, and Zephyr continue to enhance compatibility; the collaboration between commercial IP and open-source hardware and software accelerates the overall ecosystem maturity.

• Future Outlook

• With the improvement of mainstream EDA toolchains, OS support, and security certifications, RISC-V is expected to achieve breakthroughs in more high-reliability and high-performance scenarios, becoming the next “industrial-grade” ISA standard.

From initial academic experiments to the current flourishing industrial layout, RISC-V is reshaping the competitive landscape of the global chip ecosystem with its unique open-source spirit and technological advantages. In the future, with deeper collaboration between more enterprises and open-source communities, RISC-V is expected to secure a place in more vertical fields and high-end markets.You may have more content to share on this topic

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