“Seeing the dragon in the field, benefits seen by great people” — The second line of the hexagram Qian from the Book of Changes
China is one of the most important venues for the global RISC-V summit and also one of the summits with the highest participation and enthusiasm for RISC-V. Since 2021, it has been held annually, and this year marks the fifth edition. I started paying attention to RISC-V in 2017, and in 2018, I initiated an internal proposal to position RISC-V as an ISA option for our company’s chip localization strategy. In 2019, I attended the first RISC-V China Forum held in Shenzhen with colleagues. Since 2021, I have basically attended the RISC-V China Summit every year and shared insights with relevant internal leaders to continuously promote strategic updates and execution. Therefore, I have witnessed the continuous rise in scale and enthusiasm of each RISC-V summit. This year, the official estimate for participation at the RISC-V China Summit is around 2000 people on-site, but from the atmosphere, it feels like the number is much higher than last year, and the level of government leaders attending is also higher than in previous years. The main forum even invited a professional television host to moderate. In addition to inviting the CEO of RISC-V International and some foreign companies like Tenstorrent, Qualcomm, Nvidia, Infineon, giving it the significance of an international exchange platform, the summit also widely invited ecosystem partners to share and emphasize the importance of ecological collaboration. I noticed that this year’s RISC-V summit has its unique characteristics and advancements, which I will share from three aspects: “high performance,” “RISC-V + AI,” and “practical exploration.”
Figure 1 Participation numbers of previous RISC-V China Summits
I．“Without high-performance processors, there is no ecosystem”
Compared to previous years, the discussion of high-performance processors was given great importance at this summit, even overshadowing the momentum of RISC-V in the mass production of MCU/embedded products. The 2024 summit will focus more on high-performance IP and processors during the PPT phase, where CEOs from various companies passionately discussed their high-performance processor roadmaps without sharing too many details. However, this year, some demonstrations of high-performance IP and processors were already visible, and product and technology leaders from various companies were able to share detailed implementation details in the sub-forums. Although these IP and processors are still in the process of research and optimization, and their practical application and commercialization will require market validation, this indicates that RISC-V has taken a substantial step towards high-performance processors. It is expected that by the end of 2025 or early 2026, at least six RISC-V server CPUs and at least four RISC-V Client/Edge SoCs will be released, which will drive the acquisition of more high-performance development boards and further promote the development of the software ecosystem.
Figure 2 Some examples of RISC-V high-performance processors (servers and clients)
However, developing high-performance RISC-V processors still faces many challenges:
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Developing a commercially viable general-purpose server CPU generally requires a research and development cycle of 3-5 years, and RISC-V faces a significant ecological gap. Therefore, in the short term, end-users may be skeptical about adopting RISC-V general-purpose servers. This will determine that RISC-V general-purpose server chips will be a long-term investment and iteration.
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Currently, high-performance RISC-V IP is still not perfect in terms of performance, stability, toolset, and software ecosystem. High-performance edge chips with strong ecological demands, including AI PCs/Tablets, will face significant commercialization challenges in the short term and need to find suitable landing scenarios, such as some weak ecological or vertical ecological scenarios.
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Currently, there is no successful benchmark product for high-performance, similar to AWS‘s Graviton for ARM Server CPUs, or Meta-Ray Ben AI glasses for the AI glasses market, which may lead to the paradox of “the egg and the chicken.”
However, as the CEO of Nvidia stated in a recent interview with CCTV, “Innovation often arises in constrained environments, and pressure can spark brilliant ideas.” The turbulent international geopolitical environment has provided an excellent impetus and time window for China to develop high-performance RISC-V processors. With continuous iteration and the accumulation of time, RISC-V high-performance processors will undoubtedly secure a place in China.
II．Unified Promotion: RISC-V’s Opportunity for Overtaking
“Everything can be tokenized,” thus the industry has been debating whether RISC-V can adapt to the new market opportunities led by generative AI. Theoretically, RISC-V has this opportunity because it is a new type of ISA architecture that is open and customizable, but there has been a lack of rational and detailed analysis. At this summit, I was pleased to see such rational and detailed analysis:
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In terms of instruction standards for the ISA, RISC-V has finalized RVV1.0, providing more distinctive variable-length vector operations. At the same time, it is promoting the specification of instruction sets for matrix operations, with different solutions such as IME, VME, and AME under discussion.
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In analyzing the operators of large models, key operators or algorithms that determine the computational and storage requirements of large models have been identified, and optimizations have been made through RISC-V. At the same time, through the joint system design and optimization of RISC-V CPUs and acceleration units or accelerators, using AI-enhanced CPUs to offload the computations and storage of AI acceleration units or accelerators can achieve better TCO. From the summit, there seems to be a considerable consensus on this direction, but it still needs to be realized and validated in actual products.
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Some related work on the evaluation, porting, and optimization of AI software has already begun, such as Nvidia announcing that they are porting the CUDA driver to RISC-V host CPUs to better support NV’s GPU, and PLCT is also porting ROCm, with preliminary successful validation already completed.
Figure 3 Market opportunities and technical advantages and challenges of RISC-V+AI
III．Implementation: “Those who share the same desire will win”
The first principle of business, I have always believed, is “where does the money come from, and where will it go?” Therefore, a core development that determines whether RISC-V can succeed is whether more users are willing to try and ultimately pay for commercialization, as they will have a strong “pull” effect on the industry. This is another significant progress I observed at this summit. Cloud service providers such as Alibaba’s cloud department, ByteDance, and telecom operators including China Mobile and China Telecom, as well as some system integrators like HopeRun, are actively promoting the ecosystem and application innovation of RISC-V and are actively considering what scenarios are suitable for the initial landing and incubation of RISC-V. CSPs have stronger business thinking and considerations, focusing more on TCO, resource elasticity, and competitive analysis, and are beginning to conduct preliminary evaluations of RISC-V, but in terms of commercialization, they are likely to be conservative and cautious, and may become followers, needing to see some benchmark products and cases first. Meanwhile, enterprise customers are being guided to upgrade from traditional general computing to “general computing + intelligent computing,” requiring mature technology and turnkey solutions. Therefore, the adoption of RISC-V may take longer. Telecom operators, due to their strong demand for autonomy and control, and their responsibility for building an autonomous and controllable ecosystem and innovative industrial chain, are more likely to receive national support in funding, and may become important partners in building benchmark products and scenarios for RISC-V. Through system integrators of telecom operators, RISC-V solutions may also be further promoted to the government and enterprise market.
Figure 4 Different users’ demands and suggestions for potential landing points of RISC-V
Due to several sub-forums on the third day of the summit, I mainly attended two of them, and there may be important developments that I missed. I also invite friends who attended this summit to supplement and discuss in the comments section. Additionally, I did not attend the Auto sub-forum, but I have been promoting the RISC-V Auto strategy at Dajing and recognize this strategic direction. Therefore, I have been evaluating the maturity of its ecological chain and possible landing points, and I can write an article to discuss this in the future when there is an opportunity.