With the increasing scenarios for edge computing, the demand for ultra-low power CPUs is growing, requiring long-term operational capabilities, the ability to be embedded in hard-to-reach environments, and reliance on battery or ambient energy sources. A startup focused on developing high-efficiency processors, Efficient Computer, has launched a product – the Electron E1 processor and the accompanying effcc Compiler, aimed at enhancing the energy efficiency of general computing in a new way.
Electron E1 chip, image from Efficient Computer
Reconstruction Approach
For a long time, the von Neumann architecture has dominated the computing field, with its core logic being the cycle of “reading instructions from memory – processing data – writing results back to memory – reading the next instruction.” However, this model incurs significant overhead:
High Energy Consumption of Instruction Fetching:
Billions of instruction fetch operations per second consume a significant amount of energy.
Cost of Branch Prediction:
To avoid process interruptions, modern CPUs must use “branch prediction” logic to anticipate the next instruction, further increasing energy consumption and complexity.
These issues are magnified in edge computing scenarios—devices relying on limited energy face direct limitations on runtime and application scope due to inefficient energy consumption. Therefore, breaking free from the constraints of the von Neumann architecture becomes key to enhancing the energy efficiency of edge processors.
Core Architecture: Using Space Instead of Sequential Fetching
The core innovation of the E1 processor lies in its use of a “data flow architecture,” which spatially arranges program instructions on the chip, eliminating the need for sequential fetching from memory. The specific design includes:
Array of Computational Units:
Composed of a set of simplified computational units (tiles), each unit can execute instructions but omits unnecessary functions such as instruction fetching and branch prediction, retaining only core computational capabilities.
Programmable Network Connections:
The computational units are connected through specially designed programmable networks, allowing data to flow between units according to program logic, with the output of one unit directly serving as the input for the next.
Flexible Adaptation of Branch Logic:
When encountering branch statements such as if/then/else, the spatial arrangement of computational units will branch accordingly, similar to “railroad switches,” ensuring data flows along the correct path.
The accompanying “effcc Compiler” is responsible for mapping common programs like C language to hardware: allocating computational units for each instruction and configuring network paths to ensure data is processed in order. Even for arbitrary loops with feedback paths (like while loops), general computation can be achieved through architectural design—this breakthrough resolves the issue that most data flow architectures cannot support general computation. Developers do not need to change the code structure to efficiently run existing programs on the E1 architecture.
In typical embedded tasks (such as fast Fourier transforms of sensor data, machine learning convolution operations), it is claimed that the E1’s energy efficiency is 10-100 times higher than commercial ultra-low power CPUs, with two core advantages:
1. Non-intrusive adaptability: Supports C language programming, compatible with common platforms, allowing users to migrate without code restructuring;
2. Personalized optimization space: The base model has generalization capabilities, and adding a small amount of personal data can further enhance accuracy, adapting to different scenario needs.
Whether embedded in industrial devices, IoT sensors, or providing interactive tools for users with physical disabilities, it can maintain long-term stable operation under limited energy.
Significance of Release:
Providing a new paradigm for general and efficient edge computing scenarios
Unlike specific-purpose data flow architectures like Google TPU and Amazon Inferentia, the E1 possesses general computing capabilities, and its programmable network supports arbitrary control logic and loop structures, making it suitable not only for general tasks but also for AI, sensors, and other edge scenarios with high demands for low power consumption.
Simply put, this is akin to RISC-V in the embedded field, both aiming for architectural innovation to achieve efficient computing capabilities in power-constrained devices.
END
