PCB, also known as Printed Circuit Board, can connect electronic components and implement functions. It is also an important part of power circuit design. This article will introduce the basic rules of PCB layout and wiring.1. Basic Rules of Component Layout
1. Layout according to circuit modules; related circuits with the same function are called a module. Components in the circuit module should follow the proximity concentration principle, separating digital circuits from analog circuits;2. No components or devices should be mounted within 1.27mm around positioning holes, standard holes, and other non-mounting holes. For screw mounting holes, no components should be mounted within 3.5mm (for M2.5) and 4mm (for M3);3. Avoid routing vias under components like resistors, inductors (plug-in), and electrolytic capacitors to prevent short circuits between vias and component housings after wave soldering;4. The distance from the outer side of components to the edge of the board should be 5mm;5. The distance from the outer side of the mounting pad of surface-mounted components to the outer side of adjacent plug-in components should be greater than 2mm;6. Metal casing components and metal parts (such as shielding boxes) should not touch other components and should not be in close proximity to printed lines and pads, with a spacing greater than 2mm. The distance from positioning holes, fastening holes, oval holes, and other square holes in the board to the edge of the board should be greater than 3mm;7. Heating components should not be adjacent to wires and temperature-sensitive components; high-heat components should be evenly distributed;8. Power sockets should be arranged around the printed board as much as possible, and the terminals connected to the power bar should be on the same side. Special attention should be paid not to place the power socket and other soldered connectors between connectors, to facilitate the soldering and design of power cables. The spacing of power sockets and soldered connectors should consider the convenience of plugging and unplugging the power plug;9. Layout of other components: All IC components should be aligned on one side, with polarity markings clearly indicated. The same printed circuit board should not have more than two directions for polarity indications, and if two directions exist, they should be perpendicular to each other;10. The board surface wiring should be appropriately dense; if the density difference is too large, it should be filled with mesh copper foil, with a grid larger than 8mil (or 0.2mm);11. There should be no through holes on the surface-mounted pads to prevent solder paste loss causing virtual soldering of components. Important signal lines should not pass between socket pins;12. Surface-mounted components should be aligned on one side, with consistent character direction and package direction;13. Polarized components on the same board should maintain consistent polarity marking directions as much as possible.2. Component Wiring Rules
1. Define wiring zones within 1mm of the PCB edge and around mounting holes; wiring is prohibited in these areas;2. Power lines should be as wide as possible, not less than 18mil; signal lines should not be less than 12mil; CPU input/output lines should not be less than 10mil (or 8mil); line spacing should not be less than 10mil;3. Standard vias should not be less than 30mil;4. Dual in-line: pad 60mil, hole diameter 40mil; 1/4W resistor: 51*55mil (0805 surface mount); for through-hole, pad 62mil, hole diameter 42mil; non-polar capacitors: 51*55mil (0805 surface mount); for through-hole, pad 50mil, hole diameter 28mil;5. Ensure that power lines and ground lines are as radial as possible, and that signal lines do not have looped routing.How to Improve Anti-Interference Ability and Electromagnetic Compatibility?When developing electronic products with processors, how to improve anti-interference ability and electromagnetic compatibility? 1. Special attention should be paid to the following systems for electromagnetic interference resistance: (1) Systems with microcontroller clock frequencies that are particularly high and bus cycles that are particularly fast. (2) Systems containing high-power, high-current driving circuits, such as relays that produce sparks, high-current switches, etc. (3) Systems with weak analog signal circuits and high-precision A/D conversion circuits.
2. To increase the system’s anti-electromagnetic interference ability, the following measures should be taken:
(1) Choose microcontrollers with lower frequencies: selecting microcontrollers with lower external clock frequencies can effectively reduce noise and improve the system’s anti-interference ability. The high-frequency components in square waves are significantly greater than those in sine waves. Although the amplitude of the high-frequency components in square waves is smaller than that of the fundamental wave, higher frequencies are more likely to emit noise. The most impactful high-frequency noise from microcontrollers is approximately three times the clock frequency. (2) Reduce signal distortion during transmission. Microcontrollers are mainly manufactured using high-speed CMOS technology. The static input current at the signal input is about 1mA, and the input capacitance is about 10PF, which results in a high input impedance. High-speed CMOS circuits have considerable load capacity at the output, which can lead to significant signal distortion and increased system noise when a gate’s output is connected through a long line to a high input impedance. When Tpd > Tr, it becomes a transmission line issue that must consider signal reflection, impedance matching, etc. The delay time of signals on printed circuit boards is related to the characteristic impedance of the leads, which in turn is related to the dielectric constant of the PCB material. Roughly, the speed of signal transmission in PCB leads is about 1/3 to 1/2 of the speed of light. The standard delay time (Tr) for logic gate components in microcontroller systems is between 3 to 18ns. On a printed circuit board, the delay time for a signal traveling through a 7Ω resistor and a 25cm long lead is approximately 4 to 20ns. This means that the shorter the lead on the printed circuit, the better, and it should not exceed 25cm. Additionally, the number of vias should be minimized, ideally no more than two. When the rise time of the signal is faster than the signal delay time, it must be handled according to fast electronics. At this point, transmission line impedance matching must be considered. For signal transmission between integrated chips on a printed circuit board, it is important to avoid situations where Td > Trd. The larger the printed circuit board, the slower the system speed should be. The following conclusion summarizes a rule for printed circuit board design: the delay time of signal transmission on the printed board should not exceed the nominal delay time of the components used. (3) Reduce crosstalk interference between signal lines: When a step signal with a rise time of Tr at point A is transmitted through lead AB to point B, the delay time on line AB is Td. At point D, due to the signal transmission from point A to point B and the reflection of the signal at point B after Td delay, a pulse signal with a width of Tr will be induced. At point C, due to the signal transmission and reflection on line AB, a pulse signal with a width of twice the delay time on line AB (i.e., 2Td) will be induced. This represents crosstalk interference between signals. The strength of the interference signal is related to the di/at of point C and the distance between the lines. When the two signal lines are not very long, what is actually seen on AB is the superposition of two pulses. Microcontrollers manufactured using CMOS technology have high input impedance, high noise, and high noise tolerance. Digital circuits can tolerate superimposed noise of 100~200mv without affecting their operation. If AB line is an analog signal, this interference becomes intolerable. For a four-layer printed circuit board, where one layer is a large ground plane, or for a double-sided board where the signal line’s reverse side is a large ground plane, this type of crosstalk interference will be reduced. This is because a large ground plane reduces the characteristic impedance of the signal line, significantly decreasing reflection at point D. The characteristic impedance is inversely proportional to the square of the dielectric constant of the medium between the signal line and ground, and is directly proportional to the natural logarithm of the thickness of the medium. If line AB is an analog signal, to avoid interference from digital circuit signal lines CD on line AB, there should be a large ground plane below line AB, and the distance from line AB to line CD should be greater than 2 to 3 times the distance from line AB to ground. Local shielding ground can be used, with ground lines arranged on both sides of the leads where there are junctions. (4) Reduce noise from the power supply. While supplying energy to the system, the power supply also adds its noise to the supplied power. The reset line, interrupt line, and some control lines in the circuit are most vulnerable to external noise interference. Strong interference from the power grid can enter the circuit through the power supply, and even battery-powered systems can experience high-frequency noise from the battery itself. Analog signals in analog circuits are particularly susceptible to interference from the power supply. (5) Pay attention to the high-frequency characteristics of printed circuit boards and components. At high frequencies, the distribution inductance and capacitance of leads, vias, resistors, capacitors, and connectors on printed circuit boards cannot be ignored. The distributed inductance of capacitance cannot be ignored, and the distributed capacitance of inductance cannot be ignored. Resistance causes reflections of high-frequency signals, and the distributed capacitance of leads plays a role when the length exceeds 1/20 of the corresponding wavelength of the noise frequency, resulting in an antenna effect, where noise is emitted through the lead. The vias on printed circuit boards can introduce about 0.6pf of capacitance. A 24-pin dual in-line integrated circuit socket introduces 4 to 18nH of distributed inductance. These small distributed parameters can be ignored in low-frequency microcontroller systems, but they must be paid special attention to in high-speed systems. (6) Reasonable zoning of component layout. The position of components on the printed circuit board should fully consider the problem of electromagnetic interference. One principle is to keep the leads between components as short as possible. In the layout, the analog signal section, high-speed digital circuit section, and noise source section (such as relays, high-current switches, etc.) should be reasonably separated to minimize signal coupling between them. G. Properly handle grounding. On printed circuit boards, the power line and ground line are the most important. The main means to overcome electromagnetic interference is grounding. For double-sided boards, the layout of ground lines is particularly important. By using a single-point grounding method, the power and ground are connected from both ends of the power supply to the printed circuit board, with one connection for power and one for ground. On printed circuit boards, there should be multiple return ground lines that converge at the return point of the power supply, known as single-point grounding. The separation of analog ground, digital ground, and high-power device ground refers to separating the wiring, while ultimately converging at this grounding point. When connecting to signals outside the printed circuit board, shielded cables are typically used. For high-frequency and digital signals, both ends of the shielded cable should be grounded. For low-frequency analog signals, grounding at one end is sufficient. Circuits that are very sensitive to noise and interference, or circuits with significant high-frequency noise, should be shielded with metal enclosures. (7) Utilize decoupling capacitors effectively. Good high-frequency decoupling capacitors can eliminate high-frequency components up to 1GHz. Ceramic chip capacitors or multi-layer ceramic capacitors have better high-frequency characteristics. When designing printed circuit boards, a decoupling capacitor should be added between the power and ground of each integrated circuit. Decoupling capacitors serve two purposes: on one hand, they act as energy storage capacitors for the integrated circuit, providing and absorbing charge during the opening and closing moments of the circuit; on the other hand, they bypass high-frequency noise from the device. A typical decoupling capacitor in digital circuits is a 0.1uF capacitor with a distributed inductance of 5nH, whose parallel resonance frequency is approximately 7MHz, meaning it has good decoupling effects for noise below 10MHz, but almost no effect for noise above 40MHz. Capacitors of 1uF and 10uF have parallel resonance frequencies above 20MHz, which are more effective at eliminating high-frequency noise. At the point where power enters the printed board, a 1uF or 10uF high-frequency decoupling capacitor is often beneficial, even in battery-powered systems. A decoupling capacitor should be added for every 10 integrated circuits, or a charge and discharge capacitor, typically sized at 10uF. It is best to avoid electrolytic capacitors, as they are structured with two layers of rolled film, which behave as inductors at high frequencies. It is preferable to use tantalum capacitors or polycarbonate capacitors. The selection of decoupling capacitor values is not strict; it can be calculated using C=1/f; for example, 0.1uF is suitable for 10MHz, and for systems built with microcontrollers, values between 0.1uF and 0.01uF can be used.
3. Some experiences to reduce noise and electromagnetic interference. (1) Use low-speed chips instead of high-speed ones when possible; use high-speed chips only in critical areas. (2) A resistor can be used to reduce the rise and fall rates of control circuits. (3) Provide some form of damping for relays and other devices. (4) Use the lowest frequency clock that meets system requirements. (5) Place clock generators as close as possible to the devices using that clock. The quartz crystal oscillator case should be grounded. (6) Enclose the clock area with ground lines, keeping clock lines as short as possible. (7) I/O driver circuits should be placed as close as possible to the edge of the printed board, allowing them to exit the printed board quickly. Signals entering the printed board should be filtered, and signals from high-noise areas should also be filtered, while using series termination resistors to reduce signal reflection. (8) Unused pins on MCD should be connected high, grounded, or defined as output pins. All pins on integrated circuits that should be connected to power ground must be connected and not left floating. (9) Do not leave unused gate circuit input terminals floating; connect the positive input of unused operational amplifiers to ground and the negative input to the output. (10) Printed boards should preferably use 45-degree bends instead of 90-degree bends to reduce high-frequency signal emissions and coupling. (11) Printed boards should be zoned according to frequency and current switching characteristics, keeping noise components further away from non-noise components. (12) For single-sided and double-sided boards, use single-point connections for power and ground; power lines and ground lines should be as thick as economically feasible. If possible, use multi-layer boards to reduce parasitic inductance in power and ground. (13) Keep clocks, buses, and chip select signals away from I/O lines and connectors. (14) Analog voltage input lines and reference voltage terminals should be kept as far away from digital circuit signal lines, especially clocks, as possible. (15) For A/D devices, it is better to unify the digital and analog parts rather than mix them. (16) Clock lines should be perpendicular to I/O lines, as this results in less interference compared to parallel I/O lines, and clock component pins should be kept away from I/O cables. (17) Keep component pins as short as possible, and also minimize the length of decoupling capacitor pins. (18) Critical lines should be as thick as possible, with ground protection on both sides. High-speed lines should be short and straight. (19) Noise-sensitive lines should not run parallel to high-current or high-speed switching lines. (20) Do not route lines under quartz crystals and noise-sensitive components. (21) Do not form current loops around weak signal circuits and low-frequency circuits. (22) No signal should form a loop; if unavoidable, keep the loop area as small as possible. (23) Each integrated circuit should have a decoupling capacitor. A small high-frequency bypass capacitor should be added next to each electrolytic capacitor. (24) Use large-capacity tantalum capacitors or polymer capacitors instead of electrolytic capacitors for circuit energy storage. When using tubular capacitors, the casing should be grounded.
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