This is the first generation of ARM entering the V9 stage, introducing new products.
The brand new big core – Cortex X2, the brand new mid-core – A710, and the brand new small core – A510
ARM’s IPC Monster Continues – Cortex X2
First, let’s look at the performance claims:
According to this PPT, Cortex X2 has a 16% improvement in integer performance compared to Cortex X1, while floating point performance doubles.
However, upon closer inspection of the details, Cortex X1 only has 4MB of L3, while the full-fledged X1 has 8MB of L3. This is equivalent to actively lowering the performance of X1 to elevate the status of X2. However, ARM’s unequal competition between new and old products is a traditional skill, and we are used to it.
ML performance doubles.
However, whether Qualcomm will use 8MB of L3 on X2 is uncertain, as Qualcomm is notoriously good at cutting cache.
Let’s take a look at the specific improvements.
First, the optimization of branch prediction; ARM also provided a PPT for this:
In simple terms, the accuracy of branch prediction has been improved (the curve for X2 shakes wildly), which is a relatively microscopic change that cannot be intuitively reflected in the architecture diagram.
Then, the latency has been optimized, and the Buffer has been increased.
I immediately noticed that this ROB has increased by 30%; X1 was 224, and now it has increased to 288. This value even surpasses AMD’s Vermeer, which has only 256 in this aspect. Of course, compared to Firestorm’s 630 ROB, 288 still falls short.
Then there is support for SVE, with a width of 128 bits and still four FPUs.
Next, let’s look at the improvements in the backend:
The main improvements here include increasing TLB (L1 D), enlarging the Load/Store section, and enhancing data prefetching capabilities to improve memory access performance.
Basically, these are the three main improvement points. ARM also has a power consumption chart:
This chart shows that X2 has higher peak performance than X1, and beyond a certain inflection point, X2 has lower power consumption for the same performance and stronger performance at the same power consumption. The performance/power consumption curves for X2 and X1 appear to be similar, but without numerical markings, we can’t know how big the gap is after the bifurcation.
Now let’s compare the architectures of X2 and X1:
This is an identical architecture; the left one is X1, and the right one is X2.
In summary, the X2 IPC monster is an incremental update based on X1, optimizing latency, improving memory access performance, and accuracy, while also reducing the L3 of X1 by half, achieving a 16% increase in INT IPC.
As for this chart, I roughly made a reference based on it:
If it can really achieve a 16% improvement in INT IPC compared to Snapdragon 888’s X1 (with L3 being 4MB), then the INT IPC will be further close to Vortex. If Qualcomm cuts 4MB of L3 cache, it may be closer to Monsoon.
The Brand New Mid-Core – A710
Overall, the mid-core has not changed much. Since ARM has changed its approach to a big-middle-small architecture, the performance improvement of the mid-core is not the main focus. The resources for performance improvement are given as much as possible to the big core, and the improvement idea for the mid-core has become to improve performance while maintaining power consumption as much as possible, meaning the mid-core focuses more on energy efficiency and cannot be like the big core, which can be heavily stacked with cores and use higher power consumption for higher IPC.
However, it is surprising that this generation’s mid-core is not named A79 but A710. Perhaps the next generation will be called A720? It should not be called A810, as this would easily hit the ceiling.
ARM has not provided a microarchitecture diagram for A710, but it should still be optimized from the A78 architecture, which is based on the A77 framework.
This diagram summarizes the improvements in branch prediction and increased Buffer.
Like X2, this one has also optimized latency, and to enhance energy efficiency, ARM made some cuts. Perhaps due to the fact that the A77 architecture has only four decoders at the front, ARM believes that this cut would not significantly impact performance while improving energy efficiency, and at the same time, the transistors can be allocated to more useful areas.
In summary, the changes in A710 are not significant, still pursuing higher energy efficiency.
This chart can be understood as lower power consumption at the same performance, with the most ideal situation showing a 30% power consumption gap at the same performance. Meanwhile, at the same power consumption, A710’s performance compared to A78 can be expanded to a 10% difference in a certain range, although this expression is somewhat vague.
Specifically, ARM did not present intuitive IPC improvement data for A710 compared to A78 this time.
(So the biggest change for A710 should be its name.)
The Brand New Small Core – A510
The A510 is a new generation small core following ARM’s release of the A55 in 2017, and it is the legitimate successor to the A55. Before this, there was an A65 core, which had hyper-threading and was reportedly dedicated to automotive chips.
Let’s look at the details:
I can see at a glance that this is simply using a bulldozer as a template. Here is a look at the architecture diagram of the bulldozer:
The floating-point unit has an external design, with two cores sharing a set of architecture; it looks very similar.
The A510 has two cores sharing a set of architecture, but the floating-point part is independent and placed in the middle. The floating-point part also supports SVE, but only up to 2X128 bits. Currently, the design philosophy of small cores is mainly focused on heavy integer and light floating-point performance; for strong floating-point performance, it can be handled by the big core and GPU. The small core only needs to be responsible for daily use and provide considerable integer performance (many software in daily use are integer performance-oriented).
Regarding how to combine, ARM has also provided a diagram:
In 2021, even small cores are starting to pair up, while I am still alone, and only this big core still has some warmth.
Now let’s look at the front end.
At a glance, I see that the decoding width has increased, which can be positively described as a 50% increase compared to the previous generation, but negatively, it is only 3. Since I know too little about the A55, I cannot compare it.
Branch prediction is also mentioned, but no further details are provided.
The cache bandwidth has increased significantly, and since I don’t know what A55 is like, I can’t compare it; I can only look at their claims.
What I enjoy most is this straightforward IPC improvement chart:
I hope this chart does not have unfair comparisons; otherwise, A510’s actual performance may be weaker.
A510 has a 35% increase in INT performance and a 50% increase in FP performance compared to A55. What level is this?
I flipped through a lot of old charts and finally found this one:
This is the only chart where A53 appears compared to the big core. Although it’s SPEC2000, it’s better than nothing.
It is known that A55 has an 18% improvement in INT IPC compared to A53 (this is the improvement for SPEC 06).
Then, A510 improves INT IPC by 35% over A55, which means that A510’s INT IPC is 1.59 times that of A53.
If we substitute this result into the above SPEC2000, A510’s integer performance at the same frequency should be slightly stronger than A57 (the results for SPEC06 should not differ much). Therefore, the previous leak stating that the new small core’s performance matches that of the flagship A73 core seems unlikely, as A73 has an 18% improvement in INT IPC over A57, especially since Kirin 960’s A73 cores have higher frequencies than the current small cores.
We should know that Apple’s Icestorm’s INT IPC is between A76 and A77, and closer to A77. Writing this, I suddenly remember my previous conclusion that Icestorm’s INT IPC might be several times that of A55. I was foolishly hoping A510 could regain some face, but I was really naive.
ARM’s small core is likely to be used for many years, and there should be no chance to catch up in the coming years.
Well, it’s not that it can’t be used; after all, it’s a small core. The focus is on battery life, and an increase in INT performance is good enough.
In summary, the A510 small core did not bring surprises. ARM does not seem to intend to make A510 very powerful; it only aims to improve peak performance to a certain extent while ensuring that energy consumption remains at a level similar to that of A55 under low load.
If we were to summarize these three architectures,
the big and mid cores have not made major changes to the microarchitecture; the changes are relatively microscopic, focusing on optimization and buffer stacking. The execution units have not been increased. The big core’s performance has further enhanced and optimized the energy efficiency ratio, while the mid-core focuses on optimizing energy efficiency.
The small core can be said to be a completely new design. Although it is certainly sufficient for daily use, it still cannot compete with Apple, and the gap remains significant. It seems that Apple will continue to use a 2+4 configuration against Android.
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