Microcontroller Basics and Applications | Development of 8-bit Microcontrollers

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1. Development of the 80C51 Microcontroller

1. Development of the 80C51 Microcontroller

MCS-51 is the name of the microcontroller series, which includes various chip models; the 80C51 is both the series name and a specific chip model.

The early 80C51 series chip models corresponded exactly to MCS-51. They both have two sub-series, namely the basic 51 sub-series and the enhanced 52 sub-series.

The 80C51 is an improvement over MCS-51, specifically in the semiconductor integrated circuit technology used. MCS-51 uses HMOS technology, which is a high-density short-channel MOS semiconductor integrated technology, while the 80C51 uses CHMOS technology, which is a complementary metal-oxide HMOS semiconductor integrated technology. The improvement in integrated technology gives the 80C51 significant advantages such as strong anti-interference ability and low power consumption.

2. Derivative Chips of the 80C51

(1) Functionally Simplified Chips

Although the hardware and software resource configuration of the 80C51 is not high, it is still sufficient for many simple applications. To achieve optimal resource allocation and reduce costs, some simplified chips with reduced functions and structures have emerged.

The simplifications in hardware involve internal memory, timers, parallel ports, or serial ports. For example, some microcontroller applications only require a serial port and not a parallel port, so the parallel I/O content (port circuits and port line pins) can be removed, resulting in the so-called non-bus type chips without a parallel bus.

In addition to simplifying hardware, there are also simplified chips with reduced instruction sets. For instance, RISC (Reduced Instruction Set Computer) series chips produced by Microchip reduce the number of instructions and only retain some commonly used basic instructions.

(2) Functionally Enhanced Chips

To meet the needs of complex control applications, many enhanced 8-bit microcontroller chips have emerged, with enhancements including an increase in the number of timers, types of interrupts, and additional functional components.

For example, Philips’ 80C550 and 87C550 add a watchdog timer (WDT) and A/D, while the 80C552 and 87C552 add I2C, WDT, A/D, and pulse-width modulation (PWM) capabilities. Additionally, functional enhancements are also reflected in speed; for instance, the SST89E/V58RD2 chip produced by SST can reach an oscillator frequency of up to 40 MHz.

(3) Dedicated Chips

Microcontroller chips can be divided into general-purpose and dedicated types. General-purpose chips have relatively rich hardware and software resources, comprehensive performance, and strong adaptability, meeting the needs of general control applications. However, general-purpose chips have secondary development issues, requiring user-level secondary development to build a targeted practical control system.

However, in microcontroller control applications, more are dedicated chips specifically designed for certain products or specific needs. These chips are designed with considerations for the simplification of system structure, optimal utilization of hardware and software resources, reliability, and cost optimization, providing significant performance and price advantages, as well as ease of use.

2. Enhancements of 8-bit Microcontroller Functions from 8×C552

1. Hardware Structure of 8×C552

The hardware structure of the 8×C552 chip is built on the 80C51 core with additional functional components. Here, the 83C552 chip is used as an example, and the hardware structure block diagram is shown below.

(1) Basic Components of 8×C552

The hardware resources of the 83C552 chip include a central processing unit (CPU), 256 RAM units, 8 KB mask ROM, two 16-bit timers/counters (T0 and T1), a full-duplex asynchronous serial port (UART), and an externally expandable 64 KB memory space, all of which are the same as those of the 80C51 series 83C51 chip.

New functional components include: an additional timer T2, capture input/timer output logic, an A/D converter, two 8-bit frequency-divided pulse-width modulators (PWM), a watchdog timer (WDT), an interrupt structure with 15 interrupt sources, and an I2C bus interface circuit.

Additionally, the 83C552 also adds two 8-bit parallel ports P4 and P5, bringing the total number of parallel ports to six.

(2) Dedicated Registers of 8×C552

The 80C51 has only 21 special function registers (SFR), while the 8×C552 has significantly more due to enhanced functionality, reaching 56.

(3) A/D Converter of 8×C552

For control applications, the 8×C552 chip has a built-in A/D converter, consisting of an 8-channel analog input multiplexer and a 10-bit linear successive approximation A/D converter. The range of analog voltage fluctuation is 0 to +5 V, with one conversion requiring 50 machine cycles. When the oscillation frequency is 12 MHz, the conversion time is 50 μs.

When using the A/D converter, a stable power supply must be used as the reference power supply.

The registers used for A/D conversion include the high byte result register (ADCH) and the conversion control register (ADCON). The 8×C552 performs 10-bit A/D conversion, with the high 8 bits of the conversion result stored in ADCH and the low 2 bits in ADCON.

(4) Interrupt Structure of 8×C552

The number of interrupt sources for the 8×C552 has increased to 15, with the names, symbols, and vectors of each interrupt being slightly different. The interrupt system structure is shown in the diagram below.

Due to the increase in interrupt sources, both the interrupt enable register and the interrupt priority control register have increased to two. For the interrupt enable register, the original from the 80C51 is renamed IE0, and the newly added one is called IE1. For the interrupt priority control register, the original from the 80C51 is renamed IP0, and the new one is called IP1.

The hardware query order is: External Interrupt 0 (X0) → Timer 0 Interrupt (T0) → External Interrupt 1 (X1) → Timer 1 Interrupt (T1) → Serial Interrupt (S0) → I2C Interrupt (S1) → Capture 0 Interrupt (CT0) → Capture 1 Interrupt (CT1) → Capture 2 Interrupt (CT2) → Capture 3 Interrupt (CT3) → A/D Interrupt (AD) → Compare 0 Interrupt (CM0) → Compare 1 Interrupt (CM1) → Compare 2 Interrupt (CM2) → Timer 2 Interrupt (T2).

2. Event Capture and Event Timer Output

(1) Event Capture and Event Timer Output Logic

The event capture and event timer output logic of the 8×C552 consists of a 16-bit timer T2, four 16-bit capture registers, and three 16-bit comparison registers, with corresponding input and output pins. Its logic structure is shown in the diagram below.

The timer T2 is a 16-bit up counter, composed of a high byte register TMH2 and a low byte register TML2. Additionally, a prescaler is present before the timer. Timer T2 has 8-bit overflow interrupts and 16-bit overflow interrupts.

8×C552 Event Capture and Event Timer Output Logic Structure

(2) Event Capture

In the event capture logic circuit, there are four read-only 16-bit capture registers, namely CT3 (CTH3CTL3), CT2 (CTH2CTL2), CT1 (CTH1CTL1), and CT0 (CTH0CTL0). The four capture registers can capture four events, so there are four event input pins CT3I, CT2I, CT1I, and CT0I on the chip. The capture logic circuit also includes a capture control register CTCON, which stipulates the signal form of the captured events, etc. The event capture function of the 8×C552 is relatively simple, only capturing rising and falling edges of signals.

The event capture logic continuously detects external event signals. The event capture function is commonly used to measure pulse signals, including the duration of high and low levels of pulses, the number of positive and negative transitions, thus allowing the calculation of pulse frequency, period, duty cycle, and pulse count.

(3) Event Timer Output

Event timer output refers to triggering external events at pre-defined moments in the program. The timer output logic of the 8×C552 mainly consists of one time comparison circuit and three 16-bit comparison registers CM2 (CMH2CML2), CM1 (CMH1CML1), and CM0 (CMH0CML0), indicating that the 8×C552 can set up to three events at once. The state of the output event consists of a set of electrical signals, which can be set, reset, or pulse-triggered.

Event timer output has wide applications, for example:

1) Generating pulses. By controlling the level change of the pin at timed intervals, a pulse sequence can be obtained, with both pulse width and period being controllable.

2) Driving stepper motors. Stepper motors are the most commonly used actuating components in control systems, and by switching the current of each phase coil in sequence, the motor can be made to rotate stepwise. The switching of coil current can be achieved through timer output, controlling the current’s on and off using the event timer output function of the microcontroller.

3) Watchdog Timer (WDT)

(1) Monitoring Program Execution

For microcontroller application systems, reliability is crucial. This is because the field environment for microcontroller applications is often harsh, making it prone to failures due to interference; once a failure occurs, it can lead to system loss of control and even extremely serious consequences.

To improve system reliability, in addition to taking sufficient hardware measures, the execution of the program should also be monitored, as the reliability of the system ultimately reflects the execution of the program. The most common program execution faults are “runaway” and infinite loops. For these program execution faults, it is necessary to detect them in a timely manner and also be able to recover automatically to achieve system self-rescue. Common methods include inserting trap programs and setting up a “watchdog”.

1) Inserting Trap Programs

Setting traps is a purely software method. Program runaway means the program execution order is incorrect, so trap program segments can be inserted between various program modules or at the end of the program. Trap program segments usually consist of several no-operation instructions and unconditional jump instructions. Once the program runs away, it will “fall into” the trap, executing the trap program to revert to the initialization program or recovery program, thus restoring normal program execution.

2) Setting Up a “Watchdog”

The so-called “watchdog” is a metaphor for monitoring program execution. This is a combined monitoring method of hardware and software, with the hardware circuit used to sense program loss of control being compared to a “dog”. During program execution, a pulse signal (feeding the dog) is continuously sent to this circuit through instructions to maintain it in a fixed state (the dog remains quiet). When the program loses control, it cannot “feed the dog” in the specified time, and the predetermined state of the hardware circuit cannot be maintained (the dog barks).

A monostable trigger or a monostable circuit constructed from a timing circuit can be used as the “dog”, and timers can also be utilized as “dog” circuits. In the program, a fixed time interval is set to perform an initial value operation on it to maintain its non-overflow state.

(2) Watchdog Timer of 8×C552

The watchdog timer of the 8×C552 consists of an 8-bit timer T3 and an 11-bit prescaler, where the prescaler is the low part of the counting structure and the timer is the high part. The counting pulse of the watchdog timer comes from the internal clock of the chip, incrementing by one during each machine cycle.

When the watchdog timer overflows, it can generate an effective reset signal, thus resetting the microcontroller system, which is the function of the watchdog timer.

The program should assign a value to the watchdog timer within a time interval shorter than the monitoring cycle to prevent overflow. When a fault occurs and the program cannot run normally, the watchdog timer will overflow due to the inability to assign values on time, resetting the system.

4. Pulse Width Modulator (PWM)

(1) Structure of the 8×C552 PWM

The 8×C552 has two pulse-width modulation outputs, composed of a prescaler (PWMP), an 8-bit up counter, two pulse width registers (PWM1, PWM0), two comparators, and related logic circuits. Its structural block diagram is shown below.

The output pulse width interval (duty cycle) of the PWM is programmable, with data written into PWM1 and PWM0 through the program. The repetition frequency is determined by the prescaler PWMP.

(2) PWM Waveform Analysis

1) Period Adjustable

The period (or frequency) of the PWM output pulse is controlled by the prescaler PWMP. The PWM counter increments by one for each state cycle, with a maximum count value of 255 for the 8-bit counter. Therefore, the frequency f_PWM of the PWM output pulse can be calculated using the following formula:

f_PWM= f_osc/2×(PWMP+1)×255

Using this formula, as long as the clock frequency and the prescaler value are known, the PWM pulse period can be calculated in microseconds.

2) Width Controllable

The width of the PWM square wave pulse is determined by the pulse width registers (PWM1 and PWM0). Since PWM generates square waves through counting and comparison, changing the contents of the pulse width registers will change the pulse width.

3) Duty Cycle Adjustable

The percentage of the pulse width in the entire pulse period is called the duty cycle. Since the width of the PWM pulse is controllable, its duty cycle is also adjustable.

(3) Overview of PWM Applications

The most basic application of PWM is generating square waves, and the vast majority of PWM applications are based on filtering the PWM square wave. For example, by simple processing of the PWM wave, a continuously varying analog signal can be obtained, achieving D/A conversion functionality, as shown in the circuit below.

3. Flash Memory and Its Applications in Microcontrollers

Flash memory, fully known as flash programmable/erasable read-only memory, is abbreviated as flash memory or FlashROM, and can also be referred to as FPEROM (Flash Programmable and Erasable Read Only Memory). It was successfully developed by Intel in the late 1980s.

1. Overview of Flash Memory

Flash memory is writable and non-volatile, so it is commonly used as read-only memory.

In addition to having high density, low power consumption, non-volatility, high reliability, long retention time, and strong encryption capabilities, its advantages are more evident in online programming functionality.

Flash ROM and E2PROM both use electrical signals for programming and erasing, and can be repeated.

2. Flash Memory Chips

(1) Chip Packaging and Signal Pins

Flash memory chips can have storage capacities ranging from 2 to 16 KB, with recent chips appearing that have capacities from 16 to 64 MB. Here, a typical flash memory chip, the 28F010, is introduced. The storage capacity of the 28F010 flash memory chip is 128 KB, and the pin arrangement is shown in the diagram below.

The functions of each pin are as follows:

• A16～A0: Address pins. During the write cycle, their contents are latched by the internal address latch.

• DQ7～DQ0: Data pins. When the chip is not selected, the pins are in a high-impedance state.

• /CE: Chip select signal, active low. When CE=0, the chip is selected, activating the control logic and related circuits inside the chip. When CE=1, the chip is not selected, reducing power consumption to standby mode.

• /OE: Output enable control signal, active low. During the read cycle, when OE=0, the output buffer is enabled, and the read data is output through the buffer.

• /WE: Write signal, active low. Used to control write operations to the command register and storage array; the address is latched on the falling edge of WE pulse; the data is latched on the rising edge.

• VPP: Erase/program voltage.

• VCC: Main power supply, +5 V.

• VSS: Ground.

• NC: No connect pin.

(2) Hardware Structure

The core of the 28F010 is a 1,048,576-bit storage array, along with corresponding decoding and gating circuits. Other parts are auxiliary circuits for online erasing and programming. The internal hardware structure of the 28F010 is shown in the diagram below.

The structure of the 28F010 chip

Online erasing and programming are mainly achieved through the programming pin V_PP and the command register. When V_PP is not supplied with programming voltage (usually grounded), the command register content is set to the default value (i.e., data read command), and the storage chip is in read-only mode. At this point, only read operations can be performed on the flash memory, and write operations cannot be performed. To perform online erasing and programming operations, the V_PP pin must be connected to a high programming voltage (+12 V). At this time, in addition to normal data read operations on the flash memory, erasing and programming operations can also be performed, including erasing and programming the storage array and reading programming verification data. However, each operation requires writing the corresponding command to the command register.

3. Flash Microcontroller Chips

Flash microcontroller chips refer to microcontroller chips with flash memory as the internal program storage. A typical flash microcontroller chip in the 80C51 series is the 89C51.

(1) Overview of Flash Microcontroller Chips

In the development of flash microcontrollers, Atmel’s work has been particularly prominent. The 89C51 produced by the company is named with AT prefixed, referred to as AT89C51. The company’s flash microcontrollers have now been serialized as the AT89 series.

(2) Flash Microcontroller Chip AT89C51

The AT89C51 contains 4 KB of flash memory, and although performance has greatly improved, its instruction system and pins are fully compatible with the 80C51. The pins of the AT89C51 chip are shown in the diagram on the right.

The internal structure is shown in the diagram below.

The structure of the 28F010 chip

The main performance indicators and hardware resources of the AT89C51 are the same or similar to those of the 80C51 series. The main performance specifications are as follows:

• Contains 4 KB of flash memory.

• 128 B of internal RAM units.

• Two 16-bit timers/counters.

• The interrupt system still has 5 interrupt sources with a two-level priority structure.

• 4 8-bit I/O ports, i.e., 32 programmable port lines.

• Programmable full-duplex serial port.

• Wide range of operating voltage, with VCC allowing a variation range of 2.7 to 6.0 V.

• Can be set to standby and power-down states.

• Oscillator and clock circuit with full static operation mode, clock frequency can be 0 Hz to 24 MHz. Full static operation mode indicates that it does not require continuous clock timing; during waiting for internal events, the clock frequency can be reduced to 0.

(3) Simplified Chip of AT89C51

AT89C2051 (commonly referred to as 2051) is a simplified chip of the AT89C51, with only 2 KB of flash memory, and other hardware resources simplified to: 128 B of internal RAM units, 15 I/O port lines, two 16-bit timers/counters, 5 interrupt sources (two-level priority structure), a programmable full-duplex serial port, an oscillator, and a clock circuit. The pins of the AT89C2051 chip are shown in the diagram below.

The AT89C2051 does not have parallel expansion capabilities, so only P1 and P3 remain as I/O ports. However, the AT89C2051 chip includes an analog comparator, with the comparator using pins P1.1/AIN1 and P1.0/AIN0 as the positive and negative inputs for the analog signal. Since P3.6 is used as the comparator output, the chip no longer has the P3.6 pin. The diagram is shown below.

4. Programming of Flash Memory

The flash memory in the microcontroller chip is in an erased state by default, with all address units containing FFH. There are two programming methods: one is using a dedicated programming device, and the other is utilizing the system’s own resources.

Using the chip’s own resources for programming is also known as In-System Writing (ISW), or online programming.

(1) Programming Interface Signals of Flash Memory

To achieve flash memory programming, the relevant address, data, and control signals must be prepared in advance. The programming interface signals of the AT89C51 chip FPEROM are shown in the diagram below.

The functions of each pin are as follows:

• P0.7～P0.0: Code input during programming, code output during verification.

• P1.7～P1.0 and P2.3～P2.0: Address for storage array unit, since the flash capacity of the AT89C51 is 4 KB, 12 bits of address are required.

• P3.7, P3.6, P2.7, P2.6: High and low level combination settings.

• ALE/PROG: PROG is the programming pulse signal.

• EA/V_PP: VPP is the programming power supply.

For the AT89C51 chip, there are two programming voltages: one is +5 V, which can connect VPP directly to the chip’s VCC; the other is +12 V, where VPP is connected to a separate +12 V power supply. The +5 V programming voltage makes online programming of user systems possible, providing convenience for users; while the +12 V programming voltage is used for dedicated programming devices.

(2) Programming Process of Flash Memory

Taking the online programming of the flash memory in the AT89C51 user system as an example, the programming process includes the following main steps:

• Connect VPP to the +5 V power supply.
• Write the address of the programming unit.
• Write the data of the programming unit.
• Provide the necessary programming signals and level combinations.
• Issue the programming pulse.

Changing the unit address and data, and repeating the above process will complete the programming operation for the entire storage array.

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