Level Matching Issues in Circuit Design

Introduction

In circuit design, level matching is a fundamental requirement, yet it is often overlooked, which can lead to device failures and communication anomalies. In this article, we will reveal how to avoid device failures caused by level mismatches and provide practical design advice to ensure your circuit designs are both efficient and stable.

Level matching is a basic requirement in circuit design, but it can easily be overlooked, especially when the specifications of peripherals or chips are not carefully reviewed and designs are based on past experiences, leading to various issues. These problems can often be detected with a little extra scrutiny during the design phase. Below, Case 1 and Case 2 are design errors caused by not thoroughly checking the electrical characteristics of the CAN isolation module, with Case 2 being particularly subtle, involving variations in electrical characteristics at different temperatures:

MR6450 connected to a 5V CAN transceiver, operating abnormally;
Using a CAN transceiver leads to sporadic operational anomalies.

Level matching is becoming increasingly important in the design of new processor systems, as many processors now feature multiple voltage domains, with some I/O operating at 3.3V and others at 1.8V. Mismatched levels can lead to abnormal operation and even damage to I/O, such as current backflow that can harm I/O ports.

I²C level matching is also a common issue, and we will provide two different solutions for reference.

TTL and CMOS Level Parameter Definitions

Let’s first look at the definitions of TTL and CMOS logic level parameters, as shown in Figure 1.

Level Matching Issues in Circuit Design

Figure 1 TTL and CMOS Logic Level Definitions

For two devices with different logic levels to achieve reliable signal transmission, the following conditions must be met:

The output voltage VOH(MIN) of the driver must be greater than or equal to the input voltage VIH(MIN) of the receiver.
The output voltage VOL(MAX) of the driver must be less than or equal to the input voltage VIL(MAX) of the receiver.
The output voltage of the driver must not exceed the I/O voltage tolerance of the receiver.

Case 1: MR6450 UART Pin Connected to 5V Transceiver

A customer used our MR6450-L core board to connect an RS485 module via UART communication, which could not operate normally. After communicating with the customer, it was found that the RS485 module operated at a logic level of 5V.

The MR6450 core board processor is the HPM6450, whose I/O 3.3V logic level definitions are shown in Figure 2.

Level Matching Issues in Circuit Design

Figure 2 MR6450 I/O 3.3V Logic Level Definitions

The RS485 module’s 5V logic level definitions are shown in Figure 3.

Level Matching Issues in Circuit Design

Figure 3 RS485 Module 5V Logic Level Definitions

From this, it can be seen that the maximum high-level output of the HPM6450 TX signal is VCC-0.1V=3.2V, while the minimum high-level input for the 5V RS485 module TXD is 5*0.7=3.5V. It is clear that the necessary condition that the driver’s VOH must be greater than or equal to the receiver’s VIH(MIN) is not met, leading to a logic level mismatch at the I/O port and preventing communication between the two modules.

Solution:Select a 3.3V logic level RS485 module, or add a level conversion circuit between the MCU and the module.

Case 2: CAN Isolation Module Level Mismatch with Processor, Occasional Intermittent Communication Failures

The specific manifestation is that a customer used our isolated CAN transceiver module, which occasionally exhibited intermittent communication failures at room temperature. By placing the abnormal products in a high-temperature environment (65°C) for repeated power-on testing, the abnormal phenomenon could be reproduced.

At room temperature, the following signals of the abnormal products were tested: MCU power supply, TXD, CAN differential, and CAN module power supply. The normal waveforms at each point are shown in Figure 4.

Level Matching Issues in Circuit Design

Figure 4 Normal MCU, CAN Differential Signal, and CAN Module Power Supply Level Waveforms

Further high-temperature experiments were conducted. The abnormal products were placed in an oven at 65°C for repeated power-on testing, and the following signals were tested: MCU power supply, TXD, CAN differential, and CAN module power supply. The abnormal waveforms at each point are shown in Figures 5 and 6.

Level Matching Issues in Circuit Design

Figure 5 Abnormal MCU, CAN Differential Signal, and CAN Module Power Supply Level Waveforms

Level Matching Issues in Circuit Design

Figure 6 Abnormal CAN Differential Signal and CAN Module Power Supply Level Waveforms

Analysis of the waveform when the CAN bus exhibits abnormal bit width. When the TXD signal transitions from low to high, the CAN bus level remains at the dominant level. Occasionally, noise from the circuit board can cause a slight increase in the TXD level. At this point, the CAN bus level may probabilistically change to the recessive level.

In high-temperature environments, the characteristics of semiconductor materials may lead to increased power consumption of the entire system. The phenomenon presented in this case is that the MCU power supply voltage drops, while the CAN module power supply voltage rises, further affecting the logic levels of the two modules, making the abnormal phenomena more pronounced. The measured changes in the TXD high-level threshold under different voltages and temperature environments for the CAN module are shown in Figure 7.

Level Matching Issues in Circuit Design

Figure 7 Changes in TXD High-Level Threshold of CAN Module Under Different Voltages and Temperature Environments

Root Cause of the Problem:In a high-temperature environment of 65°C, the power supply of the CAN module is 5.19V, corresponding to a TXD high-level threshold of about 3.17V, while the MCU power supply is 3.08V, corresponding to a maximum I/O output voltage of about 3V. The VOH output from the MCU is below the VIH input of the CAN module, leading to a logic level mismatch between the two modules and causing communication anomalies. The logic level tolerance margin at the I/O port is relatively small; it may work at room temperature, but in strict environments such as high temperatures, the logic levels between the two modules can easily mismatch.

Solution:Replace the 5V isolation module with a 3.3V isolation module.

What to Do If I²C Levels Are Mismatched?

1. Use Dedicated I²C Bus Level Shifter Chip PCA9306

PCA9306 is a bidirectional level shifter that supports I²C and SMBus, allowing level conversion from 1.0V to 3.6V (Vref(1)) to 1.8V to 5.5V (Vbias(ref)(2)). The PCA9306 can operate at two frequencies: 400KHz and 100KHz. The maximum frequency depends on the RC time constant and generally supports >2MHz.

The standard usage circuit for PCA9306 is shown in Figure 8.

Level Matching Issues in Circuit Design

Figure 8 PCA9306 Reference Circuit

When designing, pay attention to the following points:

The voltages VREF1 and VREF2 on both sides cannot be taken arbitrarily, with VREF1 being the low voltage side and VREF2 being the high voltage side;
The EN key can be used to control the internal switch’s on and off;
The EN and VREF2 pins should be connected together;
The value of the pull-up resistor depends on the voltage drop generated when SW is on; refer to the recommended values in the manual.

2. Use MOSFETs to Build Level Conversion Circuits

The circuit shown in Figure 9 is an example of using MOSFETs for level conversion.

Level Matching Issues in Circuit Design

Figure 9 MOSFET Level Conversion Implementation

When designing, pay attention to the following points:

The low voltage side VDD_3V3 connects to the source of the MOSFET, while the high voltage side VDD_5V connects to the drain of the MOSFET;
If converting between other voltage thresholds, such as 3.3V, 2.5V, 1.8V, etc., pay attention to the Vgs turn-on voltage of the MOSFET;
This is only suitable for low-speed applications (100/400KHz).

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