RK3588 Course Series: Impedance and Parasitic Simulation Analysis

RK3588 Course Series: Impedance and Parasitic Simulation Analysis

This course series is based on the RK3588 chip as the core foundation of hardware design, using the latest version of Cadence Allegro Allegro X software to design and simulate a complete project flow for the system’s on-chip resources, interface circuit design, and various commonly used peripheral resources for chip expansion. It integrates the latest software features and techniques into daily design to reduce project redundancy and accelerate project delivery.

RK3588 Course Series: Impedance and Parasitic Simulation Analysis
RK3588 Course Series: Impedance and Parasitic Simulation Analysis

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RK3588 Course Series: Impedance and Parasitic Simulation Analysis

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Impedance and Parasitic Simulation Analysis

This course mainly focuses on the impedance analysis and parasitic parameter extraction of the RK3588 LPDDR4 high-speed transmission lines.

The example explanation section uses the Sigrity Aurora tool, which combines the user experience of Allegro with the powerful features of the Sigrity engine, allowing design teams to achieve: preliminary exploration, design, simulation analysis, final verification, and issuance of the complete design process within a single Allegro environment.

Come and click the video below to watch!

RK3588 Course Series

Exclusive tips and experience sharing live event for the last session!

September 29 (Friday) 15:00-16:00, Teacher Li Zeng will appear in the live room, explaining the impedance simulation analysis and optimization of signal transmission line impedance matching based on the RK3588 project example of LPDDR4 design using Sigrity Aurora tools, simulating and analyzing the electromagnetic coupling effects between signal lines and ground planes to determine the best line width, line spacing, and layer spacing to achieve the desired impedance value.

By adjusting line width, line spacing, and layer spacing, or adding compensation capacitors and inductors, the impact of parasitic parameters can be reduced; and signal topology information can be extracted from PCB design files. By analyzing factors such as signal paths, impedance matching, and signal coupling, accurate signal topology diagrams can be generated; understanding the signal transmission path can uncover potential signal integrity issues and allow for subsequent signal integrity analysis.

Scan the QR code below to register

RK3588 Course Series: Impedance and Parasitic Simulation Analysis

Attendance

Gift

To thank the partners for their active participation in the online live broadcast, we have prepared a [Cadence Custom Folding Umbrella] as a small gift for everyone. After the live broadcast, we will draw 10 participants who have “fully participated + valuable questions” in this live broadcast, so come and register!

RK3588 Course Series: Impedance and Parasitic Simulation Analysis

Forward

Gift

From now on, follow Bilibili 【Cadence Kaideng PCB and Packaging】, forward the 【Fifth Issue: RK3588 Project Signal Impedance, Crosstalk, Key Network Topology Link and Eye Diagram Simulation Analysis Example Skills】 registration poster dynamic and one-click triple connection to participate in the lottery activity!

We will randomly select 5 Bilibili fans to receive [Cadence Custom One-to-Three Fast Charging Data Cable].

RK3588 Course Series: Impedance and Parasitic Simulation Analysis

The deadline for this event is September 29, 2023, and the participation steps are as follows:

1. Click the button below to jump to Bilibili

Click to participate in the forwarding lottery

2. Use Bilibili account to follow 【Cadence Kaideng PCB and Packaging】 (if already followed, you can skip this step)

3. Forward the original poster dynamic and one-click triple connection to participate

Lottery Rules

1. By participating in this event, you represent that you are willing to accept the event rules, agree to our obtaining and using your WeChat nickname and Bilibili account nickname, and agree that we will contact you regarding the prize and related matters after the event.

2. All winners will be announced on or around October 12, 2023, on the “Cadence Kaideng PCB and Packaging Resource Center” WeChat official account and “Cadence Kaideng PCB and Packaging” Bilibili account.

3. After the event ends, you need to keep your WeChat contact information open. If you win, our staff will contact you within ten (10) working days after the announcement of the winners (the “redemption time”) via a WeChat survey questionnaire to confirm your mailing address. If we attempt to contact you three (3) times without success during the redemption time, it will be considered that you voluntarily give up your qualification for the prize.

4. Winners must fill in their “name, phone number, mailing address” according to the survey questionnaire requirements. In order to send you the prize, we need you to provide accurate, true, and complete contact information, including phone number and mailing address. If you fail to provide the aforementioned redemption information within the redemption time, or if the information submitted is incorrect and causes the prize to be undeliverable, we will also consider that you voluntarily give up your qualification for the prize.

5. We will mail the prizes to the address you provided, and due to traffic control and other factors, delivery may be delayed. Please be patient.

6. If you have any questions about the event rules, please send an email to [email protected] for consultation.

RK3588 Course Series: Impedance and Parasitic Simulation Analysis

RK3588 Course Series: Impedance and Parasitic Simulation Analysis

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About Yaochuang Technology
RK3588 Course Series: Impedance and Parasitic Simulation Analysis
Yaochuang Technology has accumulated over 20 years of EDA engineering service experience, providing EDA products and solutions to hundreds of customers in China, greatly improving their electronic design levels and production efficiency. Yaochuang Technology is also one of Cadence’s long-term partners in China. While introducing advanced foreign EDA tools, we have cooperated with Cadence to propose the concept of electronic and electrical collaborative design and engineering data management, which has been successfully implemented in many research institutes and commercial companies, greatly improving the standardized design process of PCB/SIP products. This covers the selection of components, collaborative design input, online inspection and analysis, standardized document output, and PLM/PDM system integration, receiving praise from many users. Meanwhile, based on the actual situation of Chinese customers, we also provide project design consulting services in addition to software training to help customers master advanced software usage while completing practical projects, which has also achieved very good results.
We always adhere to the service concept of “growing together with customers” and hope to provide support and services for more customers in the domestic EDA field!
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RK3588 Course Series: Impedance and Parasitic Simulation Analysis
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