Whether you are a logic designer, hardware engineer, or system engineer, or even hold all these titles, if you are using FPGAs in any high-speed and multi-protocol complex system, you are likely to face challenges related to device configuration, power management, IP integration, signal integrity, and other critical design issues. However, you do not have to face these challenges alone, as application engineers working at leading FPGA companies encounter these issues daily and have proposed design guidelines and solutions that will make your design work easier.
I/O Signal Distribution
FPGAs that offer the most multifunction pins, I/O standards, termination schemes, and differential pairs also have the most complex design guidelines for signal distribution. While Altera’s FPGA devices do not have design guidelines (as they are easier to implement), Xilinx’s FPGA design guidelines are quite complex. Regardless of the situation, there are some common steps to remember when assigning signals to I/O pins:
1. Use an electronic data sheet to list all planned signal distributions, along with their important attributes such as I/O standards, voltage, required termination methods, and related clocks.
2. Check the manufacturer’s block/region compatibility criteria.
3. Consider using a second electronic data sheet to develop the layout of the FPGA to determine which pins are general-purpose, which are dedicated, which support differential signal pairs, and global and local clocks, and which require reference voltages.
4. Utilize the information from the above two electronic data sheets and the area compatibility criteria to first assign the most constrained signals to pins, and finally assign the least constrained ones. For example, you may need to assign serial bus and clock signals first, as they are typically only assigned to certain specific pins.
5. Reassign the signal bus according to the level of constraint. At this stage, careful consideration may need to be given to design issues such as simultaneous switching output (SSO) and incompatible I/O standards, especially when you have many high-speed outputs or are using several different I/O standards. If your design requires local/region clocks, you may need to use pins near high-speed buses, so it’s best to remember this requirement in advance to avoid being unable to assign the most suitable pins later. If a specific block’s chosen I/O standard requires reference voltage signals, remember not to assign those pins first. Differential signal assignments should always precede single-ended signals. If an FPGA provides on-chip termination, it may also apply to other compatibility rules.
6. Assign the remaining signals appropriately.
At this stage, consider writing an HDL file that only contains port assignments. Then, by using vendor-provided tools or manually creating a constraints file with a text editor, add necessary support information for I/O standards and SSO, etc. Once you have these basic files prepared, you can run layout and routing tools to confirm whether you have overlooked any criteria or made an erroneous assignment.
This will allow you to work with layout engineers from the initial stages of design to collaboratively plan PCB routing, redundancy planning, thermal issues, and signal integrity. FPGA tools may assist in these areas and help you resolve these issues, so you must ensure you understand the capabilities of your toolkit.
The later you consult a layout expert, the more likely you are to face complex problems and design iterations that could have been avoided with some early analysis. Once you achieve satisfactory signal distribution, you should lock them in with a constraints file.
Signal Integrity
Most advanced FPGAs can handle parallel buses operating at hundreds of megahertz and serial interfaces working in the gigahertz range. At such high speeds, you need to understand the principles of signal integrity, as the handling of high-frequency signals introduces a series of analog design issues into our precise and simple digital world.
Set aside some time to read the literature provided by FPGA vendors. Even if you are well-versed in the information of a specific device or vendor, it is worthwhile to refer to documents from other vendors, as documentation from different companies often provides different insights. You will find that different vendors have varying perspectives on many issues, such as what generates high-speed signals, how much delay can exist between switching signals while still considering them simultaneous, etc. FPGA vendor tools often perform some basic signal integrity analysis well, so you must fully understand all the capabilities of the toolkit you have acquired.
Moreover, there are hundreds of books on signal integrity and noise reduction currently available on the market. If you are a beginner or need a refresher course, consider reading “Signal Integrity Issues and PCB Design” by Douglas Brooks. For a more in-depth discussion, you can read “High-Speed Digital Design” by Howard Johnson.
FPGAs may severely disrupt signals in the system (or other FPGA signals) due to excessive high-speed SSO, leading to noise known as simultaneous switching noise (SSN). SSN, also called ground bounce or VCC bounce, occurs during the process of providing transient current when outputs switch from low to high and absorbing transient current when switching from high to low, caused by multiple output drivers switching simultaneously, leading to variations in device voltage and system voltage.
Ground bounce caused by high-to-low transitions also leads to VCC droop during low-to-high transitions. Since capacitors are usually placed between VCC and ground planes, SSN typically exists in these two places. Ground bounce during low-to-high transitions may also occur. Thus, SSO becomes an interfering signal that can produce noise potentially coupling to adjacent signals. Excessive SSO in a region may disturb power supplies. SSO has become a serious issue for two reasons: 1. Switching times have drastically decreased; 2. The reduction in via sizes and trace widths, combined with greater board thickness, has increased board inductance, significantly raising the likelihood of ground bounce. Larger load capacitances may also lead to SSN, albeit to a lesser extent. When effective VCC drops below the expected value, causing the switching speed of I/O buffers to fall below the expected speed, SSN may also exacerbate timing issues.
There are several methods to reduce SSN. Some devices can simplify this issue simply by limiting the selection of I/O standards, but not all devices can do so. Some vendors recommend distributing high-speed bus outputs across the entire die; if SSN is your only concern, this is definitely a good suggestion. However, following this advice may present two fundamental problems.
First, it may lead to downstream routing issues, as spreading signals across the entire die often causes more trace crossings. This leads to a need for more signal routing layers. Secondly, most designs require careful study before spreading signals, as spreading a bus outside specific blocks or regions may lead to block/region compatibility issues. Therefore, if you can carefully distribute a smaller bus within one or two blocks/regions while considering routing, the system will work very well.
If you are troubled by a design with adjacent high-speed switching outputs, several techniques can help you address potential SSN issues. First, perform proper layout and decoupling for your design. For decoupling, use power and ground planes as close as possible, separated by an SMT capacitor. Using SMT capacitors for decoupling also helps reduce inductance, which is a major factor in generating system noise.
If you still feel the need to use decoupling capacitors (to reduce SSN), these capacitors should be placed as close to the high-speed output pins as possible. A study by Altera found that if the distance from these capacitors to the pins exceeds 1 inch, their effectiveness diminishes significantly when using appropriate SMT capacitors for decoupling. Other suggestions to reduce SSN or its potential impact include: avoiding placing sensitive signals (reset, clock, enable, etc.) near SSO; using outputs with smaller offsets and vias with the lowest inductance when possible; and inserting delays at appropriate positions to stagger output signals. Even after the PCB has been produced, this advice can still be applied.
Refer to the relevant documentation of the devices that will be connected to the FPGA. For each device, determine the maximum input low voltage threshold (in millivolts). This is the maximum voltage required for the FPGA to drive the device so that the device can still detect a valid logic low state (maximum VIL value). Similarly, determine the maximum input negative pulse signal that the device can tolerate and continue to operate (in millivolts).
In some cases, the maximum allowable ground bounce may not be or not only the values provided above. Instead, it should be determined by obtaining the minimum of the maximum input low voltage threshold, maximum input negative pulse signal, or the maximum ground bounce of all devices.
Then, group similar FPGA buses based on the number and types of networks connected with similar load characteristics. Next, study the number of power and ground pins for each section, region, or block, as well as the allowed number of SSO for each power and ground pin used for each I/O standard. These numbers can be used to calculate the total capacitive load for each group and the capacitance driven by each output to determine the maximum tolerable SSO.
You should also consult the vendor to determine whether you have exceeded the recommended number of SSO based on each block and each pair of blocks, provided that the vendor has researched these issues. Meanwhile, since multiple factors can lead to SSN, it is best to establish a robust system with built-in noise immunity. Otherwise, use devices with I/O standards limited for each pin to reduce potential SSN issues.
Differential Signals
In FPGA design, you may find the most controversy surrounding the handling of differential signals. Similar to SSO, it is best to gather as much information as possible from vendors, books, and user groups. At the same time, consult your layout department before determining a particular approach to understand their recommended advice and information.
The main debate begins with whether differential signal pairs should use wide coupling or edge coupling, and how much coupling should exist between each pair. The answer is often “it depends,” so specific studies are required.
If you cannot determine why you need to choose differential I/O standards for a single-ended signal, the answer is simple. With differential signals, you can almost completely control the return path of the signal. Because this is part of a signal pair, theoretically, there should be no current from the signal pair appearing on any ground (or power) plane.
This assumes that the trace pairs have equal lengths, are laid out in adjacent areas with consistent spacing, and have constant and matched trace impedance. Additionally, with single-ended signals, it is challenging to control the return path of the signal, and testing the return of a signal may be futile.
The main disadvantage of differential signals is that they require two traces to be in close proximity. This can be a challenge when distributing hundreds of differential signals on a PCB. But that’s a problem for the routing engineer, isn’t it?
