Cortex-X1 Microarchitecture: Bigger, Lighter, Higher Performance
While Cortex-A78 seems relatively moderate in performance targets, the biggest announcement today is the more powerful Cortex-X1. As mentioned, Cortex-X1 is a stark departure from Arm’s usual “balanced” design philosophy, with Arm-designed cores supporting absolute performance, even at the expense of energy efficiency and area efficiency.
At a high level, this design can be summarized as an overloaded A78—retaining the same functional principles but significantly increasing the structure of the core to maximize performance.
Compared to A78, its core is wider, expanding from 4 decoders to 5 decoders, increasing the renaming bandwidth to up to 8 Mops/cycle, and greatly altering some pipelines and caches, effectively doubling the NEON units and L2 and L3 caches.
At the front end (and similarly for the rest of the core), Cortex-X1 adopts all the improvements we already covered on Cortex-A78, including the new branch units. In addition to the changes introduced by A78, X1 further expands certain aspects of this module. The L0 BTB has been upgraded from 64 entries on Cortex-A77 and A78 to 96 entries on X1, allowing for more zero-latency branches. The branch target buffer still has a two-layer structure of L0 and L2 BTB, which Arm referred to in previous disclosures as nanoBTB and mainBTB. The microBTB/L1 BTB existed in A76 but has since been discontinued.
The macro-ops cache has doubled from 1.5K entries to 3K entries, which is a significant structure in the microarchitecture disclosed herein, larger than Sunny Cove’s 2.25K entries but not as large as Zen2’s 4K entry structure.
The L1I fetch bandwidth has increased from 4 instructions to 5 instructions, a 25% increase, and the decoder bandwidth has increased accordingly; the Mop cache fetch and renaming bandwidth has increased from 6 instructions to 8 instructions, a 33% increase per cycle. In fact, once it reaches the Mop cache, the core can act as an 8-wide machine.
In the core, Arm again discusses increasing dispatch bandwidth (the bandwidth of instructions per cycle) when comparing X1 to A78, with dispatch bandwidth increasing from 6 to 8, a 33% increase. In terms of µops, when breaking down Mops into smaller µops, the core can handle up to 16 dispatches per cycle, a 60% increase compared to A77’s capability of 10 µops/cycle.
The out-of-order window size has increased from 160 entries to 224, enhancing the core’s ability to extract ILP. This has been an aspect Arm has been reluctant to upgrade, as they mentioned that performance does not scale linearly with increased structure size, at the expense of power and area. Given that X1 does not have to cater to various vendors, they were able to make these concessions.
In execution, we do not see any changes in the integer pipeline compared to A78, but due to the doubling of the pipeline, the floating-point and NEON pipelines diverge more from past microarchitectures. In fact, quite literally, they can be doubled because the two existing pipelines of A77 and A78 were essentially copied and pasted, with both pairs of units functioning the same. This is a considerable improvement and increases execution resources.
In fact, Cortex-X1 is now a 4x128b SIMD machine, with vector execution width almost equal to that of some desktop cores (like Intel’s Sunny Cove or AMD’s Zen2). Although different from those designs, Arm’s current ISA does not allow a single vector larger than 128b, which is an issue that needs to be addressed in the next generation of cores.
In the memory subsystem, Cortex-X1 also underwent some significant changes. Although the AGU setup is the same as that on Cortex-A78.
In terms of L1D and L2 caches, Arm created a new design with different access bandwidths. The cache interface here is not wide, but the change is in the cache design itself, which now implements double the storage capacity. They addressed the issue of potential storage area conflicts during multiple concurrent accesses to the cache, which is a strange “zig-zag” pattern we might have observed a few years ago during memory tests on the Cortex-A76 core and still exists in some variants of that μarch.
The L1I and L1D caches on X1 should be configured to 64KB. On L2, due to it being a brand new design, Arm also took the opportunity to increase the maximum cache size, now doubling it to 1MB. This is also a new implementation, distinct from the 1MB L2 cache design we first saw on Neoverse-N1, with access latency improved by 1 cycle over N1’s 11-cycle variant, achieving 10 cycles of access latency on X1 regardless of cache size.
The memory subsystem also enhances the ability to support more loads and stores, with the window here increased by 33%, even more for the core’s MLP capability. We must note that this increase involves not only the store and load buffers but also the overall system’s ability to track and service requests.
Finally, compared to A78, the size of the L2 TLB has also doubled (a 66% increase compared to A77), providing 8MB of memory on 4K pages, ideal for the envisioned 8MB L3 cache target of the X1 implementation.
The doubling of the L3 cache in the DSU does not necessarily mean it will be a slower implementation, as latency may remain the same, but depending on the partner’s implementation, it may mean several additional latency cycles. This could refer to options for using separate power management to store L3. So far, I have not heard of any vendor using this feature of the DSU, as most implementers like Qualcomm have always kept 4MB L3 fully powered on. With the 8MB DSU, some vendors may consider better power management, such as powering it partially when only a few cores are active.
Overall, the clarity here regarding the Cortex-X1 microarchitecture is that it is primarily comprised of the same basic building blocks as Cortex-A78, but the structures are increasingly larger. Especially in the front end and core, X1 makes things significantly more complex compared to A78, with its core being a broader microarchitecture. The argument regarding the low ROI of certain structures here simply does not apply to X1, and Arm chose viable and reasonable maximum configurations, even if doing so increases the size of the core and power consumption.
I think the only real design limitation the company set here is the frequency capabilities of X1. It remains a very short pipeline design with a 10-cycle branch misprediction loss and a deep frequency design of 13 stages, remaining unchanged between A78 and X1, with the latter having a larger structure and wider design that does not hinder the peak frequency of the A78 core.
At the beginning of this article, we quickly looked at some processor performance metrics, but now we have the opportunity to delve deeper into this new CPU and more precisely define the expected performance, power consumption, and area gains that the new Cortex-A78 and X1 cores should achieve.
Starting with Cortex-A78, the comparison numbers here will be achieved in target systems on the TSMC N5 node in 2021. Thus, the numbers here incorporate both microarchitecture and expected process node improvements.
In terms of performance, setting the ISO power target for the core at 1W, Arm states that implementing A78 can yield a 20% performance increase, which is a benign upgrade. The 2.6GHz A77 on N7 roughly matches MediaTek’s Dimensity 1000(+), and the 1W power value also roughly matches what I measured on that SoC.
At the same time, through ISO performance comparisons, A78 can reduce power consumption and energy consumption by half compared to the 2.3GHz A77 on N7. This comparison may target various mid-range products on the market, which is a fair comparison, but Arm also showcased some better data that we will present later.
When comparing with ISO nodes that have similar processor configurations (basically the configuration Arm expects to be most commonly implemented), we see that A78’s performance improves by about 7% over Cortex-A77 while also reducing power consumption by 4% and area by 4%.
Arm first released an overall performance/power curve of the microarchitecture, comparing A77 with A78. We see that at higher operating frequencies, the costs are higher, and the voltage required to reach those higher frequencies (P = f * V²) also increases with the power frequency.
At the highest performance point that A77 could reach, the new A78’s power consumption will be reduced by 36%. At mid-performance levels, this power reduction will be 30%. Finally, at the same power level, A78’s performance can improve by 7%.
Now looking at Cortex-X1, the improvements in performance enhancement are even more impressive, with peak performance improving by +30% compared to A77 at the same frequency. This comparison data is based on the maximum configuration of X1 compared to A77. It is worth noting that we have never seen a vendor offer a 3GHz A77, meaning the actual performance improvement could be even greater (I expect vendors to finally achieve the 3GHz target this time).
Arm also showcased improvements in Stream bandwidth and Octane performance, although I found them not very significant, but they do serve as indicators of the microarchitecture in such workloads.
Arm is relatively vague about the power and area efficiency of X1, stating that their numbers for these “custom” parts are not as publicly available as in the Cortex-A78 roadmap design, but I was able to figure out some rough metrics. In terms of area, we expect the X1 core to be about 1.5 times the size of A78.
If vendors can effectively apply Arm’s foundational solutions and launch products on the 5nm process, we should see predictions similar to the following.
Again, these numbers are primarily predictions I derived based on various data points presented by Arm. The actual products may differ in the end, but in the past, our predictions for A76 and A77 ended up being very close to actual chip performance.
I do hope that this generation of vendors will achieve the 3GHz target for Cortex-X1, as I have heard this is one of the goals vendors aim to achieve for next year’s SoCs. I am less clear on how many vendors will base products on Cortex-A78; typically, the power consumption of Cortex-A78 will be similar to that of current A77 products (like Snapdragon 865), and vendors may leverage the last hundred MHz gain of the process to reach the 3GHz target.
The performance boost of the X1 system here will be highly competitive, being 37% faster than the current Snapdragon 865 SoC. This is a huge capability leap that will put Arm far ahead of Apple’s A13 core, although its actual competitor will be the upcoming A14.
What is truly shocking is that in terms of performance, the distance between Arm and the best desktop systems from Intel and AMD is narrowing. If these two established x86 vendors are not concerned about Arm’s annual growth rate over the past few generations, Intel and AMD should be completely alarmed if Arm truly achieves these numbers.
For many years, we have hoped for Arm to finally achieve extreme performance, and Cortex-X1 seems to be just that. It’s truly exciting.
Solution Choices and Target Customers
Naturally, Cortex-X1 is expected to be larger than Cortex-A78, but not by much. Arm does warn that for mobile designs, we do not expect to see implementations with more than two X1 cores. Essentially, Arm is embracing the industry trend of adopting a three-tier core architecture, providing customers with greater flexibility and differentiation with the launch of A78 and X1.
There will still be some customers who may be unwilling to spend money or completely opt-out of the “Cortex-X program,” and they may skip X1 and only use the A78 core. The comparison Arm makes is against an equivalent A77, and the A78 core indeed improves performance while saving significant space.
Cortex-X1 implementers are likely to choose to use a mixed cluster implementation of X1, A78, and A55 cores in the DSU. Here, Arm describes the 1+3+4 configuration favored by Qualcomm, which is the logical setup we expect to see in future Snapdragon chips.
First Impressions: Arm Finally Pursues Extreme Performance
The Cortex-A78 and Cortex-X1 released today brought unexpected surprises. I had relatively low expectations for A78, as we had long thought this would be the smallest upgrade in Arm’s CPU microarchitecture within the Austin series. After all, both A76 and A77 made significant leaps in performance.
At the same time, Cortex-X1 represents a huge change for Arm. This change is not related to core technology but more to the business decisions it now opens for the company, although the two are intertwined. For years, many have wondered why the company did not design cores that could compete more closely with Apple’s products. In my view, one reason has been Arm’s focus on designing products that meet the needs of all customers with a “one-size-fits-all core” design, rather than just a few flagship SoC designs.
The Cortex-X program effectively removes Arm’s business constraints and enables the company to offer the best of both worlds. Thus, A78 continues the company’s design philosophy of maintaining a leading position in power performance. Moreover, Arm has relentlessly beaten performance expectations, improving performance by 20-25% above expectations, a pace that currently far exceeds what competitors can achieve. These latest performance metrics are approaching the best levels seen from x86 players. This is exciting for Arm and should concern competitors.
https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging
