Exploring The Functional Safety Core Of NXP S32K3: ERM Module

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1. Overview

The NXP S32K3 series MCU is a high-performance automotive-grade MCU designed for automotive applications. This series of chips supports functional safety up to ASIL-D level and is widely used in automotive BMS, chassis controllers, body controllers, and other automotive applications. This article will introduce the ERM module in the S32K3 chip, which is one of the main modules for achieving functional safety. This module is primarily responsible for collecting memory-related errors that occur in the chip and reporting them. The following will focus on the functions of this module.

2. Main Features

The ERM module includes the following features:

• Can choose whether to generate an interrupt when an error event is captured

• Captures single-bit ECC error events and records error addresses and characteristic information, as well as captures multi-bit ECC error events

• Supports error event capture for memory, with independent reporting fields and interrupt configurations for each memory channel

• Records the number of single-bit ECC errors

The S32K3 series chips support a maximum of two ERM modules: ERM0 and ERM1.

The support for different chip platforms is shown in the table below:

The block diagram of the ERM module is shown below:

Figure 2.1 ERM Module Block Diagram

3. ERM Module Channel Mapping

Below is the mapping between different channels of ERM0 and memory areas. The complete mapping can be found in the S32K3 user manual.

Note the following points:

1. For models such as S32K342, S32K341, S32K322, S32K312, and S32K311, there is no SRAM1.

2. The cache controller will not report error addresses and error characteristic information.

3. For S32K312 and S32K211, since they only have a single core, the Cache and RAM corresponding to Cortex-M7_1 are also not present, nor is Flash Memory p2.

4. Functional Overview

The ERM module mainly includes the following registers:

• The CRn register mainly configures the interrupt notifications for each channel, including notifications for both single-bit and multi-bit error events.

• The SRn register mainly records the error events for each channel, including both single-bit and multi-bit errors.

• The EARn register mainly records the address information when an error occurs.

• The SYNn register mainly records the characteristic information of the error, identifying the relative position information of correctable single-bit data flips or uncorrectable single-bit address flips.

• The CORR_ERR_CNTn register mainly records the number of occurrences of single-bit errors.

When a single-bit error event occurs, the ERM module will perform the following actions:

1. The corresponding SBCn bit in the SRx register will be set, recording this event.

2. The error count will be increased, with the CORR_ERR_CNTn register value incremented by one.

3. The corresponding access address will be recorded and saved in the EARn register.

4. The characteristics of the ECC error, i.e., which bit is erroneous, will be stored in the SYNn register.

When an uncorrectable error event (multi-bit error) occurs, the ERM module will perform the following actions:

1. The corresponding SBCn bit in the SRn register will be set, recording this event.

2. The corresponding access address will be recorded and saved in the EARn register.

3. The characteristics of the ECC error, i.e., which bit is erroneous, will be stored in the SYNn register.

The operation flow of the ERM module is as follows:

1. Initialize the memory to known values to ensure that the correct ECC check code is stored.

2. If the ERM captures an ECC error event during memory initialization, clear the corresponding value in the SRx register.

3. Operate on the CRx[ESCIEn] and CRx[ENCIEn] register values to enable interrupts for the ERM module.

5. References

S32K3XXRM.pdf, Rev 9, 2024.07

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