Today, as AI penetrates various industries, the demand for computing power has become “extraordinarily diverse”; however, improving computing efficiency is currently challenging, and the market is fragmented with inconsistent demands. A single foundational model requires secondary development of intelligent agents tailored to specific scenarios, and the complexity and diversity of computing power deployment and scaling lead to exorbitant costs, all of which are roadblocks to the full explosion of AI.
Recently, an innovative company has proposed its solution: Him Computing has partnered with CoreLab Tech, a global leader in RISC-V CPU solutions, and Yisi Technology, a developer of RISC-V-based network chips. They aim to customize a high-performance RISC-V CPU based on Tenstorrent IP for CoreLab Tech, while collaborating with Yisi Technology to develop a high-bandwidth DPU for AI cluster interconnects. In the future, Him Computing will build a complete AI-native computing system unit consisting of self-developed “CPU + AI + DPU,” integrating a vertically developed intelligent agent platform that has been operational for a year, achieving full-scenario coverage from edge AI applications to large-scale cloud computing.
This solution is also forming a trend internationally. For example, NVIDIA’s NVL72 SuperPod integrates dozens of Blackwell GPUs and Grace CPUs, utilizing NVLink technology to achieve inter-module connectivity, forming a high-bandwidth, low-latency, and high-performance SuperPod super node, which is an ideal unit for further building large-scale computing clusters. Huawei’s recently launched Ascend CloudMatrix384 super node at the 2025 AI Conference, along with other international vendors like Tesla’s Dojo and Tenstorrent’s modular solutions, follow a similar design philosophy—efficiently interconnecting basic computing chips and CPU units to build more powerful AI subsystems.
This also means that in the various application scenarios demanding AI, whoever can more freely tailor and flexibly match computing power will take the lead.
The Strategic Value of RISC-V’s Tri-Core Synergy
From the perspective of optimizing and enhancing computing efficiency, in terms of AI chip architecture, GPUs and DSAs have largely borrowed from each other, gradually converging, with flexible Vector units paired with Tensor units becoming mainstream. The focus of enhancing computing performance and efficiency has shifted to the high integration of AI subsystems.
Focusing on the super node subsystem composed of CPU + AI + DPU, a unified architecture can achieve extreme optimization of hardware and software, making it the best solution for future intelligent computing systems. This requires the architecture to have a solid ecological foundation and a rich user base, as well as sufficient architectural flexibility to support future upgrades of AI applications and the evolution of intelligent computing systems. Relying on the same RISC-V instruction set, it will be possible to achieve unified memory access and efficient collaboration between CPU general computing units, AI dedicated acceleration units, and DPU communication units in the future, providing significant advantages in hardware and software design and ecosystem building.
From the perspective of flexibility and scalability in computing power deployment, the CPU + AI + DPU solution can push the granularity, scalability, and flexibility of the basic computing unit to the extreme through a stepwise configuration model of “single CPU → CPU + AI (direct network connection) → CPU + AI + DPU”—covering all scenario computing needs from edge to cloud while being compatible with heterogeneous environments. The series of CPU IP from CoreLab Tech complements the full specifications of DPU capabilities from Yisi Technology, adding multidimensional flexibility to AI computing units, supporting on-demand combinations of computing modules, and truly achieving modularization of AI computing power.
From the perspective of AI computing, general computing, and network interconnect collaborative design, it can address several issues in AI: first, it can optimize hardware resource allocation based on large model loads in chip design.
CPU + AI + DPU each have their specialties, avoiding functional redundancy and inefficient utilization, thus improving efficiency and reducing energy consumption. Second, collaborative design can break the limitations of traditional inefficient PCIe architectures in chip connectivity.
Third, collaborative design can achieve better granularity in AI hardware.
Due to its open-source nature, RISC-V has a natural advantage in ecology. Under the organization of the RISC-V International Foundation and the China RISC-V Working Committee, the RISC-V ecosystem, including instruction sets, simulators, compilers, and upper-layer application software and scenarios, can achieve maximum sharing. Based on this, the RISC-V computing subsystem provided by Him Computing can be easily extended to various application fields, such as embodied intelligence, industrial automation AI edge devices, workstations, and low-altitude economy.
From Edge to Cloud: The “AI Native Matrix”
To solve the “last mile” problem of AI applications in vertical fields, Him Computing has connected the entire chain from chip instruction sets to AI applications, creating a system-level landing solution for domain intelligent agents. Specifically, at the model level, the independently developed Jiuzhou large model passed national-level filing on March 31, 2025, fully adapting to government and enterprise industry applications; at the platform level, addressing pain points in the intelligent agent development process, the Qingtian intelligent agent development platform has been launched. By 2025, Him Computing has successfully implemented multiple large model intelligent agent products, providing data owners with intelligent agent development tools based on multiple models to meet the enormous inference business demands, ultimately establishing an “horizontal super node system + vertical intelligent agent development platform” AI native matrix solution.
Looking ahead, Him Computing will achieve full-scenario coverage from edge to cloud through the flexible combination of super node subsystems, empowering multiple fields with the best cost-performance and energy consumption ratios. This includes embodied intelligence, personal AI computers based on the open-source RISC-V ecosystem, integrated intelligent agent machines for edge scenarios (G-end/B-end), embedded industrial automation AI edge devices, and large-scale computing clusters in data centers. Him Computing will leverage the intelligent agent library tailored to different scenarios, fully utilizing the efficient and flexible characteristics of RISC-V, using a super node solution that combines hardware and software to provide the best answer for the development direction of RISC-V in the intelligent era!
Joining Forces to Build a World-Class RISC-V Chip System
Him Computing is a pioneer and backbone of RISC-V AI development globally, being a top-level member of the RISC-V International Foundation and undertaking many important tasks in the RISC-V international open-source community and the domestic RISC-V Working Committee. Him Computing is one of the first companies to propose the RISC-V Matrix extension plan and release related open-source implementation codes, compilers, and toolchains. The self-developed RISC-V 12nm computing chip from Him Computing has been tested by leading internet companies, achieving an average performance of 108% compared to NVIDIA’s 7nm AI chip A10. The first generation of RISC-V AI computing cards developed based on this has successfully landed multiple computing cluster projects.
Meidi, the founder of Him Computing, stated:“The core of building the RISC-V chip system lies in the intelligent computing system, and the foundation of the intelligent computing system is in node technology. As one of the earliest teams engaged in RISC-V AI chip development in China, we have accumulated a wealth of intelligent computing technology experience and are one of the few semiconductor design companies with full-stack technical capabilities from low-level instruction set design to upper-level intelligent agent development, which provides strong support for building efficient RISC-V intelligent computing node technology. Collaborating with the top CPU design team CoreLab Tech and network chip design company Yisi Technology lays a solid foundation for achieving this goal. Through the strongest R&D team, innovative business models, and precise product positioning, the three parties will jointly create a model of RISC-V cooperation, which also reflects the powerful ecological advantages of RISC-V.”
Yisi Technology has achieved remarkable results in the DPU and intelligent network card fields since its establishment in 2020. Founder Huang Yiren proposed the advanced P4 programmable DPU design concept and led the team to launch the first domestic P4 programmable intelligent network card, the Stargate series, covering multiple products from 25G to 100G, supporting virtual switching, RDMA, storage acceleration, and other scenarios, with its VLIW architecture P4 engine reaching world-leading levels. In early 2022, DPU products completed comprehensive compatibility and performance testing in customer cloud data centers, achieving breakthroughs in commercialization; in 2024, it won the “Industry Pioneer Award” and “Innovation Engine Award” in the DPU field. In 2025, the Stargate-R2100 RDMA intelligent network card, leveraging hardware engine advantages, has collaborated with multiple manufacturers and deeply participated in the open-source community, promoting the implementation of DPU technology, becoming an important force in the domestic high-performance network chip field.
Mr. Huang Yiren stated:“The strategic cooperation between Yisi Technology and Him Computing is a key milestone in the deep integration of domestic DPU and AI computing technology. We highly recognize Him Computing’s innovative strength and forward-looking layout in the AI computing field. The Yisi Technology Stargate series intelligent network cards will deeply collaborate with Him Computing’s high-performance computing chips to jointly break through the bottleneck of data center computing power. Both parties will focus on optimizing heterogeneous computing architecture, collaborative hardware and software development, and scenario implementation, providing efficient and low-consumption domestic solutions for artificial intelligence and high-performance computing fields. We look forward to accelerating the construction of autonomous and controllable computing infrastructure through this cooperation, driving the intelligent upgrade of the industry.”
CoreLab Tech, headquartered in Singapore, has a world-class processor IP team with mature experience in developing and delivering multiple generations of CPU/NPU IP, serving over 100 authorized customers globally. CoreLab Tech is committed to bridging the gap between potential and performance, becoming a trusted partner for processor technology solutions in the “last mile”.
Allen Wu, Chairman of CoreLab Tech, expressed great confidence in the collaboration, stating: “The advantage of RISC-V lies in its flexibility and efficiency. In today’s intelligent computing era, AI is ubiquitous, and the AI-native architectural design of RISC-V is its core competitiveness that distinguishes it from other technological routes. Developing high-performance RISC-V AI computing platforms requires optimizing customized computing platforms. CoreLab Tech possesses world-class RISC-V IP and customized solution engineering capabilities. Through deep cooperation with Him Computing, we will jointly create AI computing node technology, providing extreme cost-performance and usability computing products for the global market through system-level optimization and extremely detailed computing node granularity. Currently, our engineering progress is leading the world, and we look forward to the rapid launch of our collaborative products, and we are full of confidence in the future market prospects.”