Abstract: In order to obtain track information in a timely manner, a software defined radio receiver system for Automatic Dependent Surveillance-Broadcast (ADS-B) signals is designed based on the RF front-end chip AD9361 and the baseband data processing chip Zynq-7000. A detailed hardware framework design is provided, a Linux platform is established, and the AD9361 register configuration work is completed. Tests show that when the signal-to-noise ratio exceeds 6 dB, the detection probability of the receiving system exceeds 60%; during actual monitoring, the receiving system successfully receives and demodulates ADS-B short message signals with a signal-to-noise ratio of 4.4 dB. Therefore, this receiving system can be considered a well-performing ADS-B signal receiving system.

0 Introduction

Automatic Dependent Surveillance-Broadcast (ADS-B) is a surveillance technology that automatically obtains parameters from related airborne equipment and global navigation satellite systems, and broadcasts information such as the aircraft’s position, altitude, speed, and identification number to ground equipment and other aircraft. Utilizing the broadcast characteristics of ADS-B, as long as the receiving device is within the signal range, the flight data of the aircraft can be received, thus decoding the track information. In areas with complex terrain and few human activities, using ADS-B can effectively supplement track blind spots, ensuring flight safety. ADS-B technology was first successfully demonstrated at Bromma Airport in Sweden in 1991, and after strong promotion by the International Civil Aviation Organization, this technology has matured in research and application in Australia and the United States. In recent years, China has placed great importance on the research and application of ADS-B technology, and the civil aviation department has formulated ADS-B standards suitable for national conditions based on international standards, gradually promoting the application of ADS-B.

Currently, traditional low-cost receivers such as RTL-SDR and ADALM-PLUTO are based on PCs as baseband signal demodulation platforms, which have issues with portability and real-time performance; high-cost-effective receivers have good generality but are not specifically designed for ADS-B signals; while high-end receivers such as pingStation have issues with high costs and maintenance difficulties. To address these issues, this paper proposes a radio receiver based on software defined radio technology specifically for ADS-B signals.

Software defined radio technology is a technology that implements wireless communication system functions based on a general hardware platform and customized software. The characteristics of software defined radio include wide applicability, scalability, and upgradeability. Using this technology can reduce the cost of front-end receiving modules and improve R&D efficiency. This paper uses ADI’s AD9361 as the front-end signal receiving chip and Xilinx’s Zynq-7000 as the signal processing chip to design a software defined radio receiver for ADS-B.

1 Hardware Design

1.1 Software Defined Radio Transceiver System Framework

The hardware structure of this system is shown in Figure 1, where the AD9361 is connected to the Zynq-7000 via the FMC interface, and the Zynq-7000 is connected to USB, HDMI, network interfaces, etc.

The antenna receives radio signals to the RF front-end chip AD9361, which converts them into baseband signals through mixing, analog filtering, analog-to-digital conversion (ADC), and digital filtering; the baseband signals are then sent to the Zynq-7000 for data processing, where demodulation algorithms based on the corresponding modulation method convert the baseband signals into corresponding information; finally, the data is displayed via peripherals connected to the Zynq-7000. The FMC interface connecting the AD9361 and the Zynq-7000 consists of three parts: the first part is the control interface, where the Zynq-7000 configures the registers in the AD9361 via SPI or GPIO to realize the internal functions of the AD9361; the second part is the data interface, where data between the AD9361 and the Zynq-7000 is transmitted via a parallel port, which can choose low-voltage differential signaling (LVDS) or complementary metal-oxide-semiconductor (CMOS) mode to complete data reception; the third part is the clock, reset, and power interface, which mainly transmits clock signals, reset enable signals, and provides power to the AD9361.

1.2 AD9361 Receiving Signal Path Design

The receiving process structure of the AD9361 is shown in Figure 2. Due to the characteristics of ADS-B signals, the local oscillator, analog filter, and digital filter of the receiving path need to be designed.

The antenna receives wireless RF signals, amplifies them through a low-noise amplifier (LNA), and mixes the amplified signals with the local oscillator (LO) to obtain I and Q video signals. Since the center frequency of ADS-B is 1090 MHz, the LO frequency is set to 1090 MHz to down-convert the received signals to baseband signals. The down-converted baseband electrical signals are then filtered through two analog low-pass filters which reduce the level of spurious signals; the signals are then sampled through the ADC, which uses a 12-bit ADC; after conversion, the received analog signals are converted into digital signals. To meet the band-pass sampling theorem, the ADC sampling rate can be set to 160 MHz; then, the signals are filtered through three half-band filters and a programmable FIR filter, which can limit the bandwidth and suppress out-of-band noise, thus reducing spurious signals after digitization. To facilitate the calculation of the demodulation algorithm, the sampling rate is set to 20 MHz. Therefore, the sampled signal needs to be downsampled by a factor of 8 through three half-band filters. ADI has developed the AD9361 filter design wizard program in Matlab, which simplifies the FIR filter settings. Since the bandwidth of ADS-B is 2 MHz, to receive more signals, the FIR filter can be set as a low-pass filter with a passband of 4.5 MHz and a stopband of 5.5 MHz, with filter coefficients obtained through the filter design wizard program. Finally, the filtered I and Q signals are interleaved into one signal for processing by the baseband chip.

2 Software Development

2.1 AD9361 Register Configuration

The AD9361 is configured via SPI or GPIO, and generally, developers use SPI for configuration. The AD9361 has thousands of registers that can be read and written via SPI to control its operation. The AD9361 belongs to the IIO device, which is a subsystem specifically for digital-to-analog converters and analog-to-digital converters. To simplify development difficulty, ADI has developed the Libiio system based on IIO, using the library function iio_device_reg_write() to read its registers and iio_device_reg_read() to write to its registers. The internal components of the AD9361 can be divided into four categories: general settings and digital data port configuration, transmitter configuration, receiver configuration, and analog port configuration. In this system, only the signal receiving process is involved, so only general settings, digital data port, receiver, and analog port registers need to be configured. Register configuration determines the operating mode, sampling rate, filter coefficients, and a series of parameters for the software defined radio receiver, which is the core step in designing the software defined radio receiver.

2.1.1 General Settings and Digital Data Port Configuration

This group of register addresses is from 0x000 to 0x05F, mainly including chip-level settings, parallel port configuration, enable state machine (ENSM) settings, and baseband phase locked loop (BBPLL) settings.

(1) In chip-level settings, it mainly includes SPI settings, Rx enable settings, and radio frequency phase locked loop (RFPLL) divider settings.

The SPI setting address is 0x000, with a value of 0x00, enabling the most significant bit of SPI and setting the SPI_DI pin as an input pin. The Rx enable setting address is 0x003, with a value of 0xDD, enabling the Rx channel and enabling the three-stage half-band filter on this channel. The RFPLL divider register address is 0x005, with the last four bits being the value of the Rx divider. The internal voltage-controlled oscillator (VCO) of the AD9361 operates in the range of 6-12 GHz, and the VCO needs to obtain the Rx local oscillator frequency range through the divider. The formula for setting the register value is Divider Value = 2(Rx VCO Divider Register + 1).

In this formula: Divider Value is the value of the divider, Rx VCO Divider Register is the value of the last four bits of register 0x005. The local oscillator frequency required by this system is 1090 MHz, so the VCO needs to be divided by 8, resulting in a register value of 0x12.

(2) The parallel port configuration mainly sets the rate and mode of parallel data transmission ports. In this system, LVDS mode is used for data transmission, setting register 0x012 to 0x10 to use the LVDS differential mode.

(3) The ENSM settings mainly configure the operating state of the AD9361. The AD9361 has time-division duplex and frequency-division duplex modes. This system only uses the Rx signal, so frequency-division duplex mode can be used, setting the value of register 0x013 to 0x01 to enable frequency-division duplex mode.

(4) BBPLL synthesizer registers, this group of register addresses is from 0x03F to 0x04E. The baseband phase locked loop frequency synthesizer is used to generate all baseband-related clock signals, including ADC sampling clock, DATA_CLK clock, etc. The register address 0x041 stores the baseband phase locked loop frequency word in the last five bits to address 0x044, with the formula being

In this formula: BBPLLInteger is the integer part of the baseband phase locked loop frequency, floor is the floor function, fBBPLL is the frequency required by the baseband, fREF is the reference clock frequency; BBPLLFractional is the fractional part of the baseband phase locked loop frequency, fOUT is the actual output value of the baseband phase locked loop. In this system, the signal sampling frequency is set to 20 MHz, and the reference clock frequency is 10 MHz. Calculation shows that BBPLLInteger = 20, BBPLLFractional = 0, so the value of register 0x044 is 0x14, and the values of 0x041 to 0x043 are 0x00.

There are also auxiliary ADC register settings, overflow settings, and other registers in the general settings and digital data port configuration, which are not detailed here.

2.1.2 Receiver Configuration

This group of registers has addresses from 0x0F0 to 0x1FC, mainly including Rx programmable FIR filter configuration, received strength signal indicator (RSSI) measurement configuration, calibration configuration, etc.

(1) The Rx programmable FIR filter register addresses are from 0x0F0 to 0x0F6. 0x0F1 and 0x0F2 write the Rx filter coefficients, and the filter coefficients obtained from Matlab are written into these registers for configuration. Register 0x0F5 configures the filter taps and channel selection, setting the value to 0x78, enabling 64 taps and enabling channel Rx1.

(2) The RSSI measurement configuration register addresses are from 0x150 to 0x15D. This group of registers is used to measure the strength of the received signal, and the RSSI data can determine whether the corresponding signal is received. 0x158 sets the mode of the RSSI, setting it to 0x0C to enable the RSSI and initialize the RSSI measurement mode. The RSSI data reading register addresses are from 0x1A7 to 0x1AC, which are read-only registers that read the RSSI value on the Rx link.

(3) Calibration registers include orthogonal calibration registers, phase calibration registers, gain calibration registers, etc. There are many calibration registers in this part, and the default values can generally be used, which will not be detailed here.

2.1.3 Analog Port Configuration

This group of register addresses is from 0x230 to 0x3F6, mainly including Rx synthesizer register settings, digital test register settings, etc.

(1) The Rx synthesizer register is the most important part of this group of registers, mainly including VCO frequency word settings and VCO calibration settings. The VCO frequency word setting register addresses are from 0x230 to 0x235. The VCO frequency word setting is used to generate the required LO signal for the RF signal path, and the frequency synthesizer integrates an integrated VCO and loop filter. In the last three bits of register addresses 0x0231 and 0x0232, the 11-bit integer part of the VCO word is stored, while registers 0x233 to 0x235 store the 23-bit fractional part. The calculation formula for the VCO word is

In this formula: NInteger is the integer part, floor is the floor function, fRFPLL is the required local oscillator frequency, fREF is the reference clock frequency of 10 MHz, NFractional is the fractional part, Round is the rounding function. Since the standard RF frequency value for ADS-B signals is 1090 MHz, calculations show that NInteger is 109, and NFractional is 0; therefore, the value of register 0x231 is 0x6D, and the values of registers 0x232 to 0x235 are all 0x00.

2.2 Signal Demodulation Algorithm

The signal demodulation algorithm of this system is shown in Figure 3.

First, the header of the signal is detected, and the sampled signal is received. Using formula (7), the arithmetic average of the received data N is calculated to obtain the noise floor, which is then multiplied by the empirical value λ to obtain the threshold value MTL.

Search for the first sampling point that exceeds the threshold, and if the distance between the next sampling point that exceeds the threshold and the first sampling point is less than 2μs, then these two points are considered “continuous.” When a segment of “continuous” sampling points is concentrated, if the distance between the first and last points is greater than 54μs, this group of signals is sent for cross-correlation detection. The standard header sequence xn is set as [1-1 1-1-1-1-1 1-1 1-1-1-1-1-1-1], and the potential signal segment yn is cross-correlated with the standard header sequence xn using formula (8), where N is the length of the sequence.

Set the threshold to a value 6 dB higher than the noise floor amplitude, and when the cross-correlation value exceeds this threshold, search for the first peak that meets the threshold and check whether a larger peak exists within the next 3μs; if not, this point is taken as the start of the message data; if a larger peak exists, the position of the larger peak is taken as the start of the message data. After finding the header, extract the potential signal segment, and process the potential signal into a 0-1 signal based on the set threshold MTL. After completing the 0-1 processing, perform cyclic redundancy check (CRC) verification on the message part of the potential signal; if the signal passes the CRC verification, the message is translated; otherwise, the signal demodulation ends.

3 System Testing and Verification

3.1 Receiver Performance and Simulation Reception Testing

Figure 4 is the testing and verification diagram of this system, where Figure 4(a) is the actual operation diagram of the system, the antenna receives signals to the system for processing, and after demodulation, the information is displayed on the monitor via HDMI; Figure 4(b) is the performance testing diagram of the system, where the signal generator produces RF signals of different amplitudes input to the system, and the OscilloScope software is used to observe the time-domain and frequency-domain changes, completing the performance testing of the receiver.

Test results show that when the receiver bandwidth (BW) is 4 MHz, it can receive RF signals with an amplitude of -98 dBm, measuring the receiver sensitivity at -98 dBm. At a signal-to-noise ratio (SNR) of 10 dB, the noise figure (NF) of the system is derived to be approximately 4 dBm based on formula (9).

The formula for calculating the spurious-free dynamic range (SFDR) is as follows:

In this formula: the input third-order intercept point (IP3) of the receiver is 8.16 dBm, the sensitivity is -98 dBm, and the signal-to-noise ratio is taken as 10 dB. The calculated SFDR of the receiver is approximately 65 dB. Using a simulated ADS-B signal transmitter to send simulated signals with different signal-to-noise ratios to the system for demodulation, the relationship between signal-to-noise ratio and detection probability is shown in Figure 5. At a signal-to-noise ratio of 10 dB, there is nearly a 100% detection probability; at a signal-to-noise ratio of 6 dB, the detection probability exceeds 60%.

3.2 Actual Signal Reception and Analysis

To verify the system’s performance in receiving actual signals, signals were collected at latitude 32.1° N and longitude 118.51° E. Figure 6(a) shows a segment of the actual received data signal, which after demodulation contains a group of signals with a 56-bit short message ADS-B signal, as shown in Figure 6(b); Figure 6(c) shows the processed 0-1 format signal. According to the 1090ES ADS-B message standard, the message bits 1-5 indicate the downlink format segment as 01011, indicating that this group of signals is a 56-bit short message signal; bits 6-8 indicate the receiver performance segment as 101, indicating that the aircraft is airborne and has communication capability; bits 9-32 represent the International Civil Aviation Organization (ICAO) sequence number of the aircraft. The 24-bit binary ICAO number is converted into a 6-digit hexadecimal ICAO number, obtaining the ICAO number of the aircraft as 780E40. Upon inquiry, it is found that the aircraft is a Southern Airlines flight from Shenyang to Nanjing; bits 33-56 are the CRC check segment. The calculated signal-to-noise ratio for this segment is approximately 4.4 dB, indicating that this system can receive and demodulate ADS-B signals in practical applications.

3.3 Receiver Comparison

Compared to existing ADS-B receivers, this system has advantages in convenience, reliability, and cost. Compared to low-cost receivers like RTL-SDR, this system does not require PC support, offering better portability and higher sensitivity; compared to high-cost-effective receivers like ADALM-PLUTO, this system can perform real-time monitoring of ADS-B signals; compared to high-end products like pingStation, this system has similar sensitivity and dynamic range while being more cost-effective.

4 Conclusion

This paper proposes a design scheme for a software defined radio receiver specifically for ADS-B signals, detailing the hardware design and software development processes, as well as the AD9361 register configuration scheme. Through testing and verification, the system successfully received and demodulated ADS-B signals with a signal-to-noise ratio of 4.4 dB. The above conclusions indicate that this system can be reliably applied to actual signal monitoring. The algorithms used in this system still have room for improvement, but in future R&D, only slight modifications to the system application layer software algorithm program will be needed to complete system upgrades, greatly improving R&D efficiency and reducing the overall cost of equipment development. Compared to existing radio receivers, this system has better sensitivity, larger dynamic range, is specifically targeted at ADS-B signals, and is easy to build and upgrade. In summary, this system is a market-applicable ADS-B signal receiving system.

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