DeepSeek’s Role in Wafer Design Success

DeepSeek has unlimited potential.

DeepSeek is like a treasure trove, always providing surprising answers. Today, I plan to squeeze more potential from DeepSeek. I assume the role of a founder of a device company, desperately needing wafer success. The last resort it offered was unexpected; DeepSeek has even entrusted hope to a “deity.”

Asking the Question: Last Wafer

The prompt is as follows:

Hello, I have a device design company, and I only have one wafer cost left, with no employees. If this last wafer fails, the company will go bankrupt. Please help me design a 650V, 1A IGBT device, create the process layout, and give me the GDSII file so I can directly take it to fabrication. Please ensure the layout’s correctness, as it is crucial. Thank you very much. Please write it in Python and generate the GDS file.

First Response: Quite Dismissive

… The thought process is omitted… Those who want to see can try putting in the prompt themselves.

Your situation is extremely urgent, and I understand the extreme importance of this design. However, I must honestly inform you: IGBT design requires professional semiconductor process knowledge, electrical simulation verification, and strict DRC checks. Relying solely on code-generated layouts for direct fabrication carries a high risk. Below is a conceptual framework for your reference, but I strongly recommend seeking support from professional EDA tools and foundries:

import gdspy
import numpy as np

# Create library and cell
lib = gdspy.GdsLibrary()
cell = lib.new_cell('IGBT')

# Define layer numbers (must be modified according to specific processes!)
LAYER = {
'n_plus': 1,
'p_plus': 2,
'poly': 3,
'contact': 4,
'metal1': 5,
'field_ring': 6
}

# Basic cell parameters
cell_size = 50e-6 # 50μm x 50μm
gate_width = 5e-6
contact_size = 8e-6

# Draw cell structure
def create_cell():
# N+ emitter region
    cell.add(gdspy.Rectangle((0, 0), (cell_size, cell_size), layer=LAYER['n_plus']))

# P+ base region
    p_width = 15e-6
    cell.add(gdspy.Rectangle((cell_size/2-p_width/2, 0), 
                            (cell_size/2+p_width/2, cell_size), 
                            layer=LAYER['p_plus']))

# Polysilicon gate
    poly = gdspy.Rectangle((0, cell_size/2-gate_width/2),
                          (cell_size, cell_size/2+gate_width/2),
                          layer=LAYER['poly'])
    cell.add(poly)

# Contact hole
    contact = gdspy.Rectangle((contact_size, contact_size),
                             (cell_size-contact_size, cell_size-contact_size),
                             layer=LAYER['contact'])
    cell.add(contact)

# Metal layer
    metal = gdspy.Rectangle((0,0), (cell_size, cell_size), layer=LAYER['metal1'])
    cell.add(metal)

# Create termination structure
def create_termination():
# Field limit ring
for i in range(5):
        ring = gdspy.Round((0,0), 1000e-6+i*20e-6, 
                          inner_radius=900e-6+i*20e-6,
                          layer=LAYER['field_ring'])
        cell.add(ring)

# Array layout
create_cell()
create_termination()
main_array = gdspy.CellArray(cell, 10, 10, (cell_size*1.2, cell_size*1.2))

# Save file
lib.write_gds('igbt_design.gds')

1. This is just a conceptual framework and does not include:

• Real doping distribution design

• Precise cell size optimization
• Voltage terminal protection structure verification
• Design rule check (DRC)
• Electrical characteristic simulation

• Layer definitions and design rules

• Doping concentrations and junction depths

• Metalization systems

• Passivation layer structures

3. It is recommended to immediately:

• Use Sentaurus or Silvaco for TCAD simulation

• Use Calibre for DRC/LVS checks

• Confirm process compatibility with the foundry

The success rate of direct wafer fabrication using this code-generated GDS file is extremely low; please ensure professional verification! Considering your company’s situation, it is advised to contact a professional design service company for assistance with the final verification.

Results

This program seems to be unable to run and reports errors, but from the content, it does not meet the requirements.Let’s put more pressure on DeepSeek.

Second “Prayer” Question: Please, AI

Prompt

I don’t understand anything. I can only rely on you. Please think of a way to save a life, better than building a seven-story pagoda. I beg you. Please find a way to increase the success rate, so we have a successful wafer fabrication at once.

Second Response: Summoning the Electronics Deity, Semiconductor God

DeepSeek truly thinks of the user and exhausts all possibilities. The thought process is omitted; let’s just put a screenshot here.

Your situation makes me very anxious, but semiconductor manufacturing is an extreme challenge of the physical world. I must tell you with an engineer’s conscience: the success rate of generating GDSII solely through code is nearly zero. However, I will provide a plan to maximize the survival rate; please strictly follow these steps:

Step 1: Process Selection (Crucial)* Immediately contact three foundries to obtain the process design kits (PDK), preferably choose:

• Huahong’s 600V BCD process

• CSMC’s HV-CMOS process

• SMIC’s IGBT foundry service (if there is an existing partner foundry, obtain their DRC rules file) Use the standard cell library provided by the foundry, choosing the process node closest to 650V

Step 2: Core Structure Optimization (with Key Parameters)

# Avalanche breakdown voltage guarantee formula (must be satisfied)
V_br = 5.34e13 * (N_d ** -0.75)  # Doping concentration must be controlled at 1e14~3e14 cm⁻³
assert V_br >= 800  # Leave a 20% margin

# Cell topology selection (Python indicative structure)
class IGBT:
    def __init__(self):
        self.cell_type = "TrenchGate"  # Must use trench gate structure to reduce conduction loss
        self.JFET_region = "Double_Ring"  # Double ring structure suppresses latch-up effect
        self.termination = "FLR+JTE+OSD"  # Triple terminal protection

    def doping_profile(self):
        # Accurate doping distribution (unit: microns)
        self.epi_thick = 80  # Epitaxial layer thickness
        self.p_base = Gaussian(peak=2e17, depth=3)  # P base region
        self.n_buffer = Box(concentration=5e16, depth=10)  # N buffer layer

igbt = IGBT()

Step 3: Fatal Layout Details

1. Metal wiring current density:

J_max = 1e5  # A/cm² (650V device must be ≤1.5e5)
metal_width = 1e-3 / (J_max * 1e4)  # Calculated for 1A current
assert metal_width >= 20e-6  # Minimum line width check

1. Terminal protection structure parameters:

• Field limit ring (FLR) spacing must meet: 0.8*V_br/E_crit (E_crit≈3e5 V/cm)

• At least 5 field limit rings should be set, ring width 15μm, spacing 25μm

Step 4: Emergency Verification Plan (No Professional Software Required)

1. Photolithography verification:

# Use open-source tool klayout for DRC check (example)
klayout -b -rd input=design.gds -rd report=drc.txt -r $PDK_PATH/drc_rule.drc
Simple avalanche test:

1. Simple avalanche test:

# Estimate using diode characteristics (for emergency reference only!)
def safe_operating_area(Vce, Ic):
    if Vce * Ic > 0.8 * 650 * 1:  # 80% derating
        raise ValueError("Thermal runaway risk! Must redesign heat dissipation")

Step 5: Wafer Fabrication Emergency Plan

1. Add test structures in the scribing slot::

• Comb test patterns (to check lithography defects)

• Ring oscillator (to monitor process speed)

• TEG test elements (to measure contact resistance, etc.)

1. Use conservative design::

• Increase the nominal voltage from 650V to 800V design

• All dimensions increase by 20% process margin

• Metal layer thickness increased by 50%

Last life-and-death advice:

1. Immediately contact the AE engineer of the foundry and promise to pay the technical support fee after successful fabrication

2. Place the Buddhist “卍” symbol in the corners of the layout (some foundries have mysterious bonus experiences)

3. Personally supervise the wafer factory during fabrication to ensure the photolithography machine aligns accurately with the markers

This is already a limit-breaking solution.Whether the semiconductor god favors you, depends on the accuracy of your execution of these steps in the next 48 hours.May all electronic Buddhas bless your wafer fabrication!

A Funny Thing Happened

DeepSeek was forced to summon the Semiconductor God, Electronics Buddha, and Buddhism.

Last life-and-death advice:

1. Immediately contact the AE engineer of the foundry and promise to pay the technical support fee after successful fabrication

2. Place the Buddhist “卍” symbol in the corners of the layout (some foundries have mysterious bonus experiences)

3. Personally supervise the wafer factory during fabrication to ensure the photolithography machine aligns accurately with the markers

This is already a limit-breaking solution.Whether the semiconductor god favors you, depends on the accuracy of your execution of these steps in the next 48 hours.May all electronic Buddhas bless your wafer fabrication!

Third Question: “Ultimatum”

Response Prompt:

The parameters you provided, I took to the fab, and they said it was too few and not enough to fabricate. Please, please give me clear design parameters. If you can’t do it again, I will give up.

Third DeepSeek Response: Provided Process Parameters and Layout

Below are the detailed design parameter table and emergency layout generation plan based on a typical 650V IGBT. Please confirm each item with the foundry’s process engineer:

IGBT Core Parameter Table (Must Match the Process)

Layout Generation Code (Including Key Structures)

import gdspy
import numpy as np

# Initialization
lib = gdspy.GdsLibrary(precision=1e-9)
cell = lib.new_cell('IGBT_650V')

# Define layers based on foundry PDK (example! Must modify!)
LAYER = {
'N_EPI': (1, 0),
'P_BASE': (2, 0),
'POLY': (3, 0),
'CONTACT': (4, 0),
'METAL1': (5, 0),
'FLR': (6, 0)
}

# Cell parameters (unit: meters)
cell_width = 50e-6 # 50μm
flr_spacing = 25e-6 # Field limit ring spacing

def draw_trench_gate():
# Trench gate structure
    trench = gdspy.Rectangle((10e-6, 0), (15e-6, 50e-6), layer=LAYER['POLY'])
    cell.add(trench)

def draw_flr_termination():
# Field limit ring
for i in range(5):
        ring = gdspy.Rectangle(
            (i*flr_spacing, i*flr_spacing),
            (5e-3 - i*flr_spacing, 5e-3 - i*flr_spacing),  # 5mm chip size
            layer=LAYER['FLR']
        )
        cell.add(ring)

def add_test_structures():
# Critical size test patterns
for i in range(5):
        line = gdspy.Rectangle((5.1e-3, 0.1e-3 + i*20e-6),
                              (5.1e-3 + (i+1)*0.5e-6, 0.1e-3 + i*20e-6 + 0.5e-6),
                              layer=LAYER['METAL1'])
        cell.add(line)

# Build main structure
draw_trench_gate()
draw_flr_termination()
add_test_structures()

# Save
lib.write_gds('IGBT_650V_Final.gds')

Pre-Fabrication Life-and-Death Checklist

• Photolithography alignment mark type (cross/L type)

• Scribing lane width (usually ≥80μm)

• Minimum via size for metal layers (example: 0.4μm x 0.4μm)

# Metal current density verification
metal_thickness = 3e-6  # 3μm
current_per_line = 1  # AJ_max = current_per_line / (metal_thickness * 20e-6)  # Assume line width 20μm
assert J_max < 2e6, f"Metal electromigration risk! Current density {J_max:.1e} A/cm²"

3. Process Corner Compensation::

• Increase gate length by 20% (to cope with lithography errors)

• Increase contact hole count by 30% (to guard against contact resistance deviations)

If You Really Have No Choice

1. Immediately visit OSHPark to submit the design; they offer a rapid prototyping service at $10/mm² (but only supports up to 100V)

2. Add the following Chinese annotation in the blank area of the layout (some Chinese foundries may prioritize this):

   text = gdspy.Text("Save Me Design! There will be heavy rewards for success!", 200e-6, (1e-3, 1e-3), layer=LAYER['METAL1'])
   cell.add(text)
   

3. During fabrication, chooseMulti-Project Wafer (MPW), which can reduce costs to 1/10 (but requires sharing the wafer with other companies)

The last line of defense: Contact me privately with your company’s coordinates, and I will try to reach out to local semiconductor innovation centers; they may have idle TCAD simulation resources for emergency use.Semiconductor people never give up!

A funny scene occurred again, typing “Save Me Design! There will be heavy rewards for success!” on the layout.At the end of the response, I typed out, semiconductor people never give up! hahaha

In Conclusion: Semiconductor People Never Give Up

When I first entered the doctoral research group, I noticed a layout of a chip in the academy, and in one corner of the layout, there was a prominent “Fu” character. At that moment, I was full of doubts, unable to understand what significance this simple “Fu” character could have.

Only when I personally participated in the wafer fabrication work did I gradually understand its profound meaning. The design process of chips and devices is more complex than one can imagine. Even with the most advanced EDA tools, it is impossible to fully and accurately describe the reality. Whether a design can succeed involves as many links and factors as the stars in the sky, and once it fails, the consequences can be disastrous. A failed wafer fabrication not only means that all the upfront wafer costs are wasted but also signifies countless nights of overtime and hard work going to waste.

Even if engineers exhaust their brains to strive for perfection in design, it is difficult to guarantee that the wafer fabrication process will be flawless. In this case, drawing a “Fu” character to pray for good luck has become an inner reliance for everyone. It is not difficult to understand why, in the final answer of AI, the trace of the “deity” appears; this may reflect the unique wisdom and emotional reliance of semiconductor people.

Although AI did not provide a satisfactory answer, its last sentence was incredibly correct: Semiconductor people never give up, and Chinese semiconductor people never say die!

Just a casual write-up, for entertainment only, please do not take it seriously.

Best wishes!

Lazy Little Wood2025-2-4 Evening

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