Have you heard about the recent launch of several new CPUs on the market? Their performance is quite powerful! Yes, we are talking about the ARM Cortex-A75 and Cortex-A55, the first processors in the Cortex-A series based on the newly released DynamIQ technology. For detailed information about the Cortex-A75, click here→In-depth article! Everything you want to know about ARM’s latest high-performance processor Cortex-A75 is here. This time, we will discuss why the Cortex-A55 is a crucial processor for the future digital world.
Born from a Noble Lineage, Time-Tested
Higher performance meets the demands of AI tasks, which are a major focus of current and future ARM IP.
To understand the true potential of the Cortex-A55, let’s briefly review its predecessor: the ARM Cortex-A53. Devices using this CPU have exceeded 1.5 billion units, and it remains the highest-selling 64-bit Cortex-A series CPU in the industry today. The Cortex-A53 was released in 2012, and its unique design, which combines performance, low power consumption, and size scalability, features a range of versatile characteristics, making it applicable in various markets, including high-end smartphones, network infrastructure, automotive infotainment, advanced driver-assistance systems (ADAS), digital TVs, entry-level mobile devices, consumer electronics, and even satellites.
However, many changes have occurred in our world since 2012. The emerging trends we now see indicate that maintaining a connected, intelligent digital world has tremendous growth potential. From fully autonomous self-driving cars to intelligent applications on various devices, artificial intelligence (AI) and machine learning (ML) are set to be integrated into our daily lives. The prevalence of Internet of Things (IoT) applications signifies explosive growth in ‘things’, with an increasing number of ‘things’ continuously generating, consuming, and interacting with data. Augmented reality, virtual reality, and mixed reality (AR, VR, and MR) are destined to radically change the way we interact with each other and between humans and machines, merging the real world with the digital one.
In the past two years, ARM engineers have worked diligently on the successor to the Cortex-A53 to meet the demands of these emerging technologies. Our goal was to create a CPU with significantly improved performance, efficiency, and scalability, while also incorporating many advanced features to meet the future application needs from edge to cloud. Fortunately, we have succeeded.
Comprehensive Performance Enhancements
The Cortex-A55 achieves comprehensive performance improvements
The Cortex-A55 is built on the latest ARMv8.2 architecture and is developed based on its predecessor. It breaks performance limits while maintaining the same power consumption level as the Cortex-A53. We have made every effort to improve the Cortex-A53 and equipped it with the following features:
➤ Memory performance can reach up to twice that of Cortex-A53 under the same frequency and process conditions
➤ Efficiency is 15% higher than Cortex-A53 under the same frequency and process conditions
➤ Scalability is over ten times that of Cortex-A53
These improvements are attributed to our focus on the existing design concepts of Cortex-A53 and challenging those concepts:
1
The branch predictor has been comprehensively modified, incorporating neural network elements into its algorithm to improve predictions. Additionally, a zero-cycle branch predictor has been introduced to further reduce bubbles in the pipeline, minimizing idle time between instructions.
2
Our design makes the secondary cache dedicated for each CPU, which reduces access time by over 50% compared to Cortex-A53. We also designed the secondary cache to operate at the same frequency as the CPU, significantly enhancing CPU performance across various benchmark tools by reducing latency.
3
A tertiary cache has been introduced, shared among all Cortex-A55 CPUs within a cluster. This allows the DynamIQ cluster to benefit from increased memory capacity near the CPU, thus enhancing performance and reducing system power consumption. The tertiary cache is part of the DynamIQ Shared Unit (DSU), a new functional unit within DynamIQ processors.
4
8-bit integer matrix multiplication impacts neural network performance by over 85%. A new architectural instruction has been added to the Cortex-A55 NEON pipeline, enabling it to perform 16 instances of 8-bit integer operations per cycle. These new instructions also allow the CPU to execute 8 instances of 16-bit floating-point operations per cycle and perform rounding on two MAC instructions, facilitating color space conversions.
Significant Efficiency Improvements Over Cortex-A53
The Cortex-A55 maintains a leading position in power and thermal efficiency
The aforementioned improvements in the branch predictor, NEON, and FP units, along with reduced memory latency, are just part of the reasons for the significant performance gains of the Cortex-A55. Not only has the Cortex-A55 achieved substantial performance improvements, but it has also maintained similar power consumption levels to the Cortex-A53. Overall, the Cortex-A55 has achieved a 15% improvement in energy efficiency. In product design, power is more critical than performance. Under equivalent performance, the Cortex-A55 consumes 30% less power than the Cortex-A53!
The Cortex-A55 provides sustained performance for a longer duration than today’s Cortex-A53 solutions. This is crucial for user experiences in fields like AR, VR, and MR, which are expected to dominate the future mobile market. These use cases are highly threaded and have strict latency requirements. The latter refers to mobile latency, which, according to industry research, needs to be maintained at 20 milliseconds or below to avoid causing nausea and dizziness. While today’s CPUs have achieved the performance levels necessary to reach 20 milliseconds of latency, thermal limitations mean these CPUs cannot sustain such performance levels for long periods. With the Cortex-A55, we can provide a solution that extends sustained performance times in future VR devices.
Advanced features and higher performance can meet the demands of the infrastructure market
The industry-leading efficiency of the Cortex-A55 sets it apart in the infrastructure market, allowing applications such as Power over Ethernet (PoE) wireless access points and thermal-limited automotive solutions installed in rearview mirrors to leverage the Cortex-A55’s high thermal efficiency to provide maximum performance within specific thermal ranges. In 5G remote radio heads (RRH), the Cortex-A55 CPU can also maximize network throughput within specified power ranges.
From Edge to Cloud
Appropriate size and computing performance can meet various needs
In addition to performance and efficiency, the physical chip size and computing performance of the Cortex-A55 also offer high scalability. To this end, it includes multiple RTL configuration options, allowing configurable capacity to reach ten times that of the Cortex-A53. In fact, it boasts over 3,000 unique configurations, making it the most scalable Cortex-A CPU ever.
The Cortex-A55 retains the flexibility of the Cortex-A53, featuring options such as NEON, Crypto, and ECC (Error Correction Code), but also adopts new practical configuration options. For instance, the configurable capacity of the dedicated secondary cache ranges from 64KB to 256KB, providing a 10% performance boost. The dedicated secondary cache significantly enhances performance and is undoubtedly set to become the default choice across many markets, designed as an option to further reduce chip size in IoT and other size-sensitive markets.
Details on new features in the DynamIQ Shared Unit (DSU)
The DSU is common in both Cortex-A55 and Cortex-A75. It includes more configuration options that can be customized based on the user’s application scenarios. For example, the shared tertiary cache between CPUs can expand from 0KB to a maximum of 4MB. It also supports multi-purpose interface options through AMBA 5 ACE or CHI, making it applicable to a wider range of systems. Accelerator coherence ports (ACP) and low-latency peripheral ports (PP) are also integrated into the DSU, allowing tightly-coupled accelerators to connect to the Cortex-A55 for general-purpose computing. These features, combined with the machine learning capabilities of the Cortex-A55, enable more computations to be executed closer to the edge of IoT gateway applications.
Incorporating Numerous Advanced Features for Various Emerging Applications
Accelerating AI applications across various fields
Artificial intelligence is becoming increasingly ubiquitous, and this is no longer news. Consequently, running machine learning tasks on our devices will also become quite common. There are various ways to implement machine learning processing on a chip; however, CPUs have unique advantages in this regard. CPUs can perform general-purpose computing, allowing them to run AI applications on the chip. Currently, as machine learning and AI continue to evolve, fixed-function hardware is not only expensive but also prone to obsolescence for machine learning.
Improvements to the Cortex-A55 NEON pipeline and the addition of new machine learning instructions mean that the Cortex-A55 significantly outperforms the Cortex-A53 in matrix multiplication operations for machine learning. The recently released ARM Compute Libraries, optimized specifically for ARM Cortex-A NEON and Mali GPU IP, can also be applied to Cortex-A55 NEON to further enhance its machine learning performance!
The Cortex-A55 can create safer autonomous systems
The reliability, availability, and serviceability (RAS) features of the Cortex-A55 are also high, allowing it to serve various fields, including infrastructure and automotive. For the automotive market, the safety of the Cortex-A55 has been enhanced. It provides optional ECC and parity features on every level of cache and supports data poisoning, a method that delays detected uncorrectable errors, suitable for more resilient systems. It is also the first Cortex-A series CPU to adopt a new design process to avoid system failures, making it well-suited for ASIL D applications when paired with the Cortex-R52.
Deeply Embedded Advanced Power Management Features
Advanced power management features enhance energy efficiency
The Cortex-A55 features numerous new power characteristics, such as hardware-controlled state transitions that allow for faster switching from ON to OFF. The Cortex-A55 can also autonomously disable the tertiary cache based on the currently running applications. For heavy-load applications requiring more memory, such as VR, the tertiary cache will be fully enabled. However, for lightweight applications like music playback, which reside entirely in the primary and secondary caches, the tertiary cache will be disabled. Additionally, there are two power modes for applications between heavy and light loads.
It is now also possible to create single CPUs or CPU clusters, where each CPU operates within its own independent voltage domain within the cluster, allowing for more precise dynamic voltage and frequency scaling. This has two significant benefits: First, it allows designers to further tune the system for optimal performance and energy efficiency. Second, it means that DynamIQ systems can more easily match the varying thermal limits of devices, maximizing performance.
A New Era of big.LITTLE Processing
The big.LITTLE technology has been synonymous with heterogeneous processing since its introduction in 2011. Today, two out of every three Android ARMv8 devices on the market rely on big.LITTLE technology to achieve power and performance optimization. DynamIQ big.LITTLE is the next generation of heterogeneous computing technology within the DynamIQ system.
It allows designers to create fully integrated solutions using Cortex-A75 ‘big’ CPUs and Cortex-A55 ‘little’ CPUs, with both types of CPUs physically located within a single CPU cluster. All software thread migrations and the resulting cache snooping between the big and little CPUs now occur within that cluster. Compared to the Cortex-A73, the Cortex-A75 CPU can be utilized in higher frequency scenarios while still maintaining continuous DVFS curves with the Cortex-A55. This is a significant design requirement of the big.LITTLE system. Together, these features can greatly enhance peak performance, sustained performance, and intelligent capabilities compared to the previous generation of big.LITTLE technology.
DynamIQ big.LITTLE brings a richer user experience
Today, mid-range mobile and consumer markets widely adopt 4-core and 8-core solutions based on Cortex-A53. However, as advanced use cases like AI and VR penetrate the mid-range market from the high-end market, manufacturers need to provide higher performance and intelligent capabilities at a lower cost. DynamIQ big.LITTLE meets this demand by introducing new heterogeneous CPU configurations, such as 1 Cortex-A75 + 3 Cortex-A55 (1 big + 3 little) and 1 Cortex-A75 + 7 Cortex-A55 (1 big + 7 little), etc. These new configurations can achieve more than double the single-thread performance compared to 4-core and 8-core Cortex-A55 designs at similar chip sizes.
Infrastructure and Mobile SoC Design Guidelines Now Available
ARM has long invested heavily in validating our intellectual property through example SoC designs. As ARM’s intellectual property portfolio continues to grow, the complexity and scope of these reference systems also increase. This work covers everything from SoC architecture to detailed pre-production analysis. ARM will provide this knowledge in the form of “system guidelines”.
In addition to the new CPUs, ARM also offers various new system guidelines covering mobile and infrastructure systems:
➤ The CoreLink SGM-775 system guideline for mobile systems is specifically designed and optimized for Cortex-A75, Cortex-A55, and Mali-G72.
➤ SGM-775 includes documentation, models, and software, and is available for free to ARM partners.
When Can We Expect Devices Based on Cortex-A55 to Be Released?
The final release of the Cortex-A55 is exciting. The significant progress in performance, energy efficiency, and scalability will make the Cortex-A55 ARM’s next best-selling Cortex-A series CPU. However, the excitement doesn’t stop there; many ARM partners within this ecosystem have already obtained licenses for the Cortex-A55, and we look forward to seeing what new wave of intelligent computing solutions they will release in the coming months. While we cannot predict how devices based on the Cortex-A55 will manifest, one thing is certain: the future starting in 2018 will be incredibly exciting!
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