The Jingxin SoC training camp has students asking how to load the waveform in the task function in Verdi. Here, we will introduce it using the high-speed image interface MIPI as an example.
We create a task function for the MIPI DSI protocol to test. The function code is as follows:
Configuring MIPI DPHY requires multiple configurations, so we need to call the task function multiple times to configure MIPI DPHY. Therefore, we encapsulate it again. The code is as follows:
However, the task function cannot see its internal signal waveforms in Verdi. How can we check if the DPHY configuration is correct by observing the waveforms?
The solution is simple. Please move to the knowledge star discussion, modify the simulation options, and you will be able to see the internal signal waveforms of the task, as shown in the figure below, consistent with the task function execution.
The Jingxin Micro SoC team business
Introduction to the Jingxin Micro SoC team business:
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Providing SoC, MCU, ISP, CIS, and other chip design services
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Providing chip design, verification, DFT, and full-process backend design services
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Providing backend design processes including 7nm, 12nm, 28nm, 40nm, 55nm, 65nm, 90nm, 110nm, 180nm nodes, offering cost-effective chip manufacturing channels
The Jingxin SoC training camp allows everyone to design their own SoC/MCU chip!
Recruiting outstanding trainees to join our design outsourcing team for part-time project work!
[The only one on the internet] Jingxin SoC is a low-power ISP image processing SoC used for full-process chip training, using a low-power RISC-V processor, with built-in ITCM SRAM, DTCM SRAM, integrating IPs such as MIPI, ISP, USB, QSPI, UART, I2C, GPIO, Ethernet MAC controller, designed using SMIC40 process.
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CPU: RISC-V
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ITCM: 64KB
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DTCM: 64KB
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Peripherals: MIPI/USB/HDMI/UART/I2C/QSPI
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System Clock: 100MHz
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MIPI RX decoding
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ISP image processing
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HDMI interface
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High-speed interface Verilog design implementation -
Image algorithms and Verilog design implementation -
MIPI communication protocol’sVerilog implementation -
Lint, CDC checks andUVM verification -
Post-simulation
The content of just one frontend course is equivalent to 5-6 courses from other training institutions.
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DFT design (chip-level) -
Synthesis logic synthesis (chip-level) -
Low-power UPF design, CLP technology -
formal verification and other technologies
(3) SoC Backend Course, You Will Learn
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Layout and routing (low-power FF flow) -
StarRC/QRC -
STA/Tempus -
Power analysis -
DRC/LVS design
The content of just one backend course is equivalent to 3-4 courses from other training institutions.
The course provides servers for everyone to practice! It will take you from algorithms, frontend, DFT to backend full-process participation in SoC project design. For more content, please contact the author to register, log in to the server for practice, the engineering data is divided into the following three parts.
Data path for image processing:
CRG design of Jingxin SoC:
One-click completion of C code compilation, simulation, synthesis, DFT insertion, formal verification, layout and routing, parasitic parameter extraction, STA analysis, DRC/LVS, post-simulation, formal verification, power analysis, etc. The upgraded chip design engineering V2.0 flow is as follows:
SoC one-click execution flow
MIPI DPHY+CSI2 decoding
Classic design in digital circuits: Implementation of multiple communication data Lane Merging design
Classic design in digital circuits: Implementation of multiple communication data Lane Distribution
UPF low-power design
Full-chip UPF low-power design (including DFT design)
Before low-power design, the power consumption was 28.75W
After low-power design, during sleep, the power consumption was 21.45mW, reduced by 7mW
Chip layout design V1.0
Chip layout design V2.0
The DRC/LVS of low-power design, the LVS of the chip top layer is very challenging! Unique experience sharing in the industry.
ISP image processing
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dpc – Bad pixel correction
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blc – Black level correction
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bnr – Bayer noise reduction
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dgain – Digital gain
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demosaic – Demosaicing
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wb – White balance gain
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ccm – Color correction matrix
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csc – Color space conversion (RGB2YUV conversion formula based on integer optimization)
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gamma – Gamma correction (brightness based on table lookup gamma correction)
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ee – Edge enhancement
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stat_ae – Automatic exposure statistics
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stat_awb – Automatic white balance statistics
CNN image recognition
Supports handwritten digit AI recognition:
Simulation results: The simulation recognizes the digits 7, 2, 1, 0, 4, 1, 4, 9 in the image above.
CPU Startup Instruction Analysis
Frontend Design Directory
Mid-level Design Directory
Backend Design Directory
Welcome to join the 【Full-Stack Chip Engineer】 knowledge star to discuss technology, exchanging the full process design from algorithms, frontend, DFT to backend.Click the image below to join the knowledge star!
Welcome to join the CIS+ISP technology exchange group, add my WeChat first, and I will pull you into the group!
Welcome to join the MCU chip design exchange group, add my WeChat first, and I will pull you into the group!
