The integrated MIPI DPHY MCU layout designed by the editor is as follows, and today we will sort out the integration verification of DPHY.
Drive strength:
Used to represent the strength of 0: highz0, supply0, strong0, pull0, weak0.
Used to represent the strength of 1: highz1, supply1, strong1, pull1, weak1.
Strength decreases in the order of supply, strong, pull, weak. Note that supply0 and supply1 are used for model power, which can only provide 0 and 1 values for the net, usually only used in the standard cell library provided by the Vendor and not used in normal times.
For example, the drive strength of the DP and DN interfaces of the MIPI DPHY testbench in HS mode, LP mode/ULPS mode is as follows. In simulation mode, to make the HS drive strength the strongest, we use supply to drive bufif1, and then use pull to drive bufif1 in LP mode.
Taking the dphy_ipi_tests test as an example, the specific simulation driving functions are as follows:
The initialize_dut function initializes the DUT:
phy_testclr = 1'b1; phy_testdin = 8'd0; phy_testen = 1'd0; phy_testclk = 1'd0; presetn= 1'd0; #(10) presetn= 1'd1; #(10) update_phy_test_ctrl1; update_phy_test_ctrl0;Assign initial values (invalid values) to the following registers:
task update_phy_test_ctrl0; apbWrite(`CSI2_HOST_PHY_TEST_CTRL0_OS, {30'd0, phy_testclk, phy_testclr});endtask task update_phy_test_ctrl1;apbWrite(`CSI2_HOST_PHY_TEST_CTRL1_OS,{15'd0, phy_testen, 8'd0, phy_testdin});endtask
Note that the phy_test_ctrl1 register is used for DPHY configuration:
//CSI2 Controller ProgrammingapbWrite(`CSI2_HOST_PHY_SHUTDOWNZ_OS, 32'hFFFF_FFFF); // Cancel phy shutdownapbWrite(`CSI2_HOST_DPHY_RSTZ_OS , 32'hFFFF_FFFF); // Cancel phy resetapbWrite(`CSI2_HOST_CSI2_RESETN_OS , 32'hFFFF_FFFF); // Cancel csi2 resetConfigure the DPHY bandwidth to 1GHz, and configure the interface timing as follows:
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