1. Characteristics of the RISC-V Instruction Set
(1) Open Source Nature and Community-Driven:The instruction set architecture is open source,adopting a permissive BSD license, with characteristics of the BSD license introduced in(Hard Ten Huashan Development Board Series (7): Open Source Innovation, Closed Source Delivery). Companies can use it freely and at no cost, and they are also allowed to add their own instruction sets without the need to share them, which promotes rapid ecosystem development and high community activity.
(2) Modular Design:The RISC-V architecture is compact and its different parts can be combined in a modular way, with the RISC-V instruction set using letters to define a module. Refer to the table below, the most basic and only mandatory part of the instruction set is represented by the letter I, which denotes the base integer instruction subset (e.g., RV32I), while other instruction subsets are optional modules, including M (multiplication and division instructions), A (atomic operation instructions), F (single-precision floating-point instructions), D (double-precision floating-point instructions), C (compressed instructions), etc. As RISC-V continues to evolve, the status of these instruction sets is also changing.
Users can flexibly choose different module combinations to meet their customized device needs, for example, for small area low-power embedded scenarios, users can choose the RV32IC combination instruction set, using only Machine Mode; while for high-performance application operating system scenarios, they can choose the RV32IMFDC instruction set, utilizing both Machine Mode and User Mode.
(3) Simple Instruction Set:The streamlined instruction set improves the efficiency of instruction pipelining and reduces the complexity of instruction decoding and execution. The development of X86 and ARM architectures has also accompanied the continuous maturation of modern processor architecture technology, but as commercial architectures, they must retain many outdated definitions to maintain forward compatibility, leading to a large number of instructions, instruction redundancy, and a vast amount of documentation, making it challenging to develop new operating systems or applications on these architectures. In contrast, the emerging RISC-V architecture sheds these burdens and constructs its instruction set based on mature aspects of computer architecture, setting off light..
(4) Scalability:The instruction set allows users to define custom extensions to meet specific application needs and adapt to changing scenarios.
(5) Platform Independence:The instruction set design is independent of the hardware platform and can be used for various hardware implementations, from embedded systems to high-performance servers.
(6) Support for Multiple Data Widths: Supports processing of different data widths (such as 32-bit, 64-bit, and 128-bit), suitable for various application needs.
(7) Low Power Design: Optimizes power efficiency, making it suitable for applications with high power requirements, such as mobile devices and embedded systems.(8) A Broad Ecosystem: A wide ecosystem has been established, including processor cores, operating systems, compilers, development toolchains, and hardware-software solutions. Currently, RISC-V support has been integrated into major tools, such as the GCC compiler toolchain and QEMU simulation tools; in terms of operating system adaptation, RISC-V provides privileged and user-level instructions, along with detailed instruction specifications, enabling developers to easily port Linux and UNIX systems to the RISC-V platform.2 Why Should Chinese Developers Choose RISC-V? Developers ask why they should use a new instruction set? As discussed in RISC and RISC-V, the instruction set is the source of the software ecosystem, while the chip hardware is merely the hardening of software. Assuming a CPU company wants to design a new CPU and launch it in the market, it must start with designing the instruction set. First, a new instruction set ISA is designed, a CPU compatible with this ISA is manufactured, and then the produced CPU is installed in a computer, followed by the development of related operating systems, compilation software (also known as toolchains), etc., providing a usable platform for application software developers. For Chinese developers and companies, we entered the market later on X86 and ARM, and RISC-V presents a rare opportunity. Because China’s chip design started late, and the design of processor chips is the crown jewel of the chip industry. Currently, the companies that have successfully commercialized and occupy the core control position in the industry are mostly from Europe and the United States, such as Intel, AMD,NXP etc., which have already formed a large and complete ecological chain. Therefore, from a commercial perspective, to compete with these traditional powers, we must find opportunities in “new trends, new applications, new platforms.” One approach is to build a new instruction set architecture from scratch, and then launch processor hardware, gradually increasing the number of software that can run on this new hardware platform, thereby expanding its ecosystem, but this path is difficult and time-consuming. Another approach is to choose a platform like RISC-V that is in a period of growth, using it as the basis for the instruction set to launch hardware and build an ecosystem, fully leveraging its open-source nature, strong scalability, and the already forming ecosystem, making this path of leveraging opportunities more likely to succeed for industry challengers.
Academician of the Chinese Academy of Sciences and computer expert Ni Guangnan predicted at the 2022 RISC-V China Summit that RISC-V will develop into one of the world’s mainstream CPU architectures, representing an important opportunity for China’s chip industry to gain initiative. Data shows that by 2025, the number of chips using the RISC-V architecture will increase to 62.4 billion. At the same time, RISC-V is penetrating from the fragmented and customized IoT field into high-performance computing areas such as mobile devices, HPC, and servers. Currently, high performance is a direction that needs to be broken through, and many companies both domestically and internationally have released mass-producible high-performance RISC-V chips, but entering the mainstream CPU server field still has a long way to go. Ni Guangnan pointed out that the rapid development of RISC-V is likely to form a triopoly with Intel’s X86 and ARM, presenting significant opportunities in this direction!
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