1. Explanation of Some Common English Abbreviations in ARM
MSB: Most Significant Bit;
LSB: Least Significant Bit;
AHB: Advanced High-performance Bus;
VPB: VLSI Peripheral Bus connecting on-chip and off-chip peripherals;
EMC: External Memory Controller;
MAM: Memory Accelerator Module;
VIC: Vector Interrupt Controller;
SPI: Serial Peripheral Interface;
CAN: Controller Area Network, a serial communication protocol;
PWM: Pulse Width Modulator;
ETM: Embedded Trace Macrocell;
CPSR: Current Program Status Register;
SPSR: Saved Program Status Register;
2. Notes on Using MAM:
Answer: When changing the MAM timing value, you must first disable MAM by writing 0 to MAMCR, then write the new value to MAMTIM. Finally, write the corresponding value for the desired operation mode to MAMCR to enable MAM again.
For system clocks below 20MHz, set MAMTIM to 001. For system clocks between 20MHz and 40MHz, it is recommended to set Flash access time to 2cclk, and for system clocks above 40MHz, use 3cclk.
3. Notes on Using VIC
Answer: If the code is running in on-chip RAM and the application needs to call interrupts, the interrupt vector must be remapped to Flash address 0x0. This is because all exception vectors are located at address 0x0 and above. This can be achieved by configuring the MEMMAP register (located in the System Control Module) to User RAM mode. User code is linked to load the interrupt vector table at 0x4000 0000.
4. ARM Boot Code Design
Answer: The ARM boot code is programmed directly for the processor core and hardware controllers, usually using assembly language. The boot code generally includes:
Interrupt vector table
Initializing memory system
Initializing stack and special requirement ports/devices
Initializing user program execution environment
Changing processor mode
Calling the main application
5. Difference Between IRQ and FIQ
Answer: IRQ and FIQ are two programming modes of the ARM processor. IRQ refers to interrupt mode, while FIQ refers to fast interrupt mode. For FIQ, you must handle your tasks quickly and exit this mode. IRQ can be interrupted by FIQ, but IRQ cannot interrupt FIQ. To make FIQ faster, this mode has more shadow registers. FIQ cannot call SWI (software interrupt). FIQ must also disable interrupts. If an FIQ routine must re-enable interrupts, it is too slow and should be IRQ instead of FIQ.
6. ARM Processor’s Response to Exception Interrupts
Answer: The ARM processor’s response to exception interrupts is described as follows:
Save the current state of the processor, interrupt mask bits, and various condition flags;
Set the corresponding bits in the Current Program Status Register CPSR;
Set the lr_mode register to the return address;
Set the Program Counter PC to the interrupt vector address of the exception interrupt and jump to the corresponding exception interrupt for execution.
7. Difference Between ARM Instructions and Thumb Instructions
Answer: In the ARM architecture, instructions in the ARM instruction set are 32-bit instructions with high execution efficiency. For application systems with a 16-bit data bus, the ARM architecture provides a Thumb instruction set. The Thumb instruction set is a re-encoded subset of the ARM instruction set, with an instruction length of 16 bits. Typically, when the processor executes ARM programs, it is said to be in ARM state; when executing Thumb programs, it is in Thumb state. The Thumb instruction set does not change the program design model of the ARM architecture but adds some constraints to that model. The operands for data processing instructions in the Thumb instruction set are still 32 bits, and the instruction addressing is also 32 bits.
8. What is ATPCS
Answer: To enable inter-calling between separately compiled C language programs and assembly programs, certain rules must be established for subroutine calls. ATPCS is the basic rule for subroutine calls between ARM programs and Thumb programs. These rules include register usage rules, data stack usage rules, and parameter passing rules.
9. Scenarios for Mixing ARM and Thumb Programs
Answer: Generally, Thumb programs are more compact than ARM programs, and for systems with 8-bit or 16-bit memory, using Thumb programs is more efficient. However, in the following scenarios, programs must run in ARM state, thus requiring a mix of ARM and Thumb programs.
In speed-critical scenarios, ARM programs should be used;
Some functions can only be completed by ARM programs, such as enabling or disabling exception interrupts;
When the processor enters an exception interrupt handler, the program state switches to ARM state, meaning that some instructions at the entry of the exception interrupt handler are ARM instructions. Then, as needed, the program can switch to Thumb state, and before returning from the exception interrupt program, switch back to ARM state.
The ARM processor always starts execution in ARM state. Therefore, if you want to run a Thumb program in a debugger, you must add an ARM program header to that Thumb program before switching to Thumb state to execute the Thumb program.
10. ARM Processor Operating Modes
Answer: The ARM microprocessor supports 7 operating modes, which are:
User Mode (usr): The normal program execution state of the ARM processor;
Fast Interrupt Mode (fiq): Used for high-speed data transfer or channel management;
External Interrupt Mode (irq): Used for general interrupt handling;
Supervisor Mode (svc): The protected mode used by the operating system;
Data Abort Mode (abt): Entered when a data or instruction prefetch aborts, used for virtual storage and storage protection;
System Mode (sys): Running privileged operating system tasks;
Undefined Instruction Abort Mode (und): Entered when an undefined instruction is executed, which can be used for software emulation of hardware coprocessors.
11. Types of Exceptions Supported by the ARM Architecture
Answer: The exceptions supported by the ARM architecture and their specific meanings are as follows (the numbers in parentheses indicate priority):
Reset (1): When the reset level of the processor is valid, a reset exception occurs, and the program jumps to the reset exception handler (exception vector: 0x0000,0000);
Undefined Instruction (6): When the ARM processor or coprocessor encounters an unprocessable instruction, an undefined exception occurs. This exception mechanism can be used for software emulation (exception vector: 0x0000,0004);
Software Interrupt (6): Generated by executing the SWI instruction, it can be used for privileged operation calls in user mode programs. This exception mechanism can be used to implement system function calls (exception vector: 0x0000,0008);
Instruction Prefetch Abort (5): If the address of the prefetch instruction does not exist or is not allowed for the current instruction to access, the memory will send an abort signal to the processor, and the instruction prefetch abort exception will occur when the prefetch instruction is executed (exception vector: 0x0000,000C);
Data Abort (2): If the address of the data access instruction does not exist or is not allowed for the current instruction to access, a data abort exception occurs (exception vector: 0x0000,0010);
IRQ (4): When the external interrupt request pin of the processor is valid, and the I bit in CPSR is 0, an IRQ exception occurs. The system’s peripherals can use this exception to request interrupt service (exception vector: 0x0000,0018);
FIQ (3): When the fast interrupt request pin of the processor is valid, and the F bit in CPSR is 0, an FIQ exception occurs (exception vector: 0x0000,001C).
Note: The exception vector 0x0000,0014 is a reserved exception vector.
12. Memory Format Supported by the ARM Architecture
Answer: The memory formats supported by the ARM architecture are as follows:
Big-endian format: The high byte of word data is stored at a low address, and the low byte of word data is stored at a high address;
Little-endian format: Opposite to big-endian storage format, the high address stores the high byte of data, and the low address stores the low byte of data.
13. ARM Register Summary:
ARM has 16 32-bit registers (r0 to r15).
r15 acts as the program counter PC, r14 (link register) stores the return address of subroutines, and r13 stores the stack address.
ARM has one current program status register: CPSR.
Some registers (r13, r14) will produce new instances when an exception occurs, such as in IRQ processor mode, where the processor uses r13_irq and r14_irq.
ARM’s subroutine calls are very fast because the return address of the subroutine does not need to be stored on the stack.
14. Reasons for Memory Remapping:
To ensure that the FIQ handler in Flash memory does not need to consider memory boundary issues caused by remapping;
To greatly reduce the use of SRAM and Boot Block vectors for handling code space segment boundary arbitration;
To provide space for jumps exceeding the single word transfer instruction range to save constants.
Remapping in ARM refers to reallocating its memory address space mapping during program execution by writing to a functional register bit. A typical application is that the application program is stored in Flash/ROM, and initially these memory addresses start from 0; however, the read time of these memories is longer than that of SRAM/DRAM, resulting in low internal execution frequency. Therefore, it is generally necessary to move the code to SRAM/DRAM in the preceding program segment, then remap the memory space, mapping the corresponding SRAM/DRAM to address 0, and re-executing the program to achieve high-speed operation.
15. Reasons for Using LDR Instruction for Program Jumps in the Exception Vector Table Instead of B Instruction:
The LDR instruction can jump across the entire address range, while the B instruction can only jump within a range of 32MB before and after;
The chip has a Remap function. When the vector table is in internal RAM or external memory, the B instruction cannot jump to the correct position.
16. Key Points on Phase-Locked Loop (PLL):
PLL is disabled and bypassed during chip reset or entering low power mode, and will not automatically restore PLL settings after waking from low power;
PLL can only be enabled via software;
After activation, PLL must wait for it to lock before it can connect;
Improper PLL settings can lead to incorrect chip operation.
17. Differences Between ARM7 and ARM9:
ARM7 core has a 0.9MIPS/MHz three-stage pipeline and von Neumann architecture; ARM9 core has a five-stage pipeline, providing 1.1MIPS/MHz Harvard architecture.
ARM7 does not have an MMU, while ARM720T has an MMU; ARM9 has an MMU, and ARM940T only has a Memory Protection Unit, not a complete MMU.
ARM7TDMI provides an excellent performance-to-power ratio. It includes the Thumb instruction set, fast multiplication instructions, and ICE debugging technology. ARM9 has a higher clock frequency than ARM7 and uses Harvard architecture to differentiate between data and instruction buses.
18. Basic Operations of VIC are as Follows:
Answer: Set IRQ/FIQ interrupts; if it is an IRQ interrupt, it can be set as a vector interrupt and assigned an interrupt priority, otherwise it is a non-vector IRQ. Then, interrupt enabling can be set, along with the corresponding address for vector interrupts or the default address for non-vector interrupts. When an interrupt occurs, if it is an IRQ interrupt, the vector address register can be read, and then jump to the corresponding code. When exiting the interrupt, write 0 to the vector address register to notify VIC that the interrupt has ended. When an interrupt occurs, the processor will switch modes, and the relevant registers will also be mapped.
19. Notes on Using External Interrupts
After setting a pin to external interrupt functionality, that pin is in input mode. Since there is no internal pull-up resistor, an external pull-up resistor must be connected to ensure the pin is not floating;
In addition to setting the pin connection module, the VIC module also needs to be configured to generate external interrupts; otherwise, external interrupts can only be reflected in the EXTINT register;
To allow the device to enter low power mode and wake up via external interrupts, the software should correctly set the external interrupt functionality of the pin before entering low power mode.
20. Basic Operation Methods for UART0
Set I/O connections to UART0;
Set serial port baud rate (U0DLM, U0DLL);
Set serial port working mode (U0LCR, U0FCR);
Send or receive data (U0THR, U0RBR);
Check serial port status word or wait for serial port interrupt (U0LSR).
21. Basic Operation Methods for I2C
Answer: Basic operation methods for I2C master:
Set I2C pin connections;
Set I2C clock rate (I2SCLH, I2SCLL);
Set as master and send start signal (I2CONSET’s I2EN and STA bits are 1, AA bit is 0);
Send slave address (I2DAT), control I2CONSET to send;
Determine bus status (I2STAT) to control data transmission;
Send end signal (I2CONSET).
