Introduction to STM32
The STM32 series is based on the ARMCortex®-M0, M0+, M3, M4, and M7 cores specifically designed for embedded applications that require high performance, low cost, and low power consumption. Prior to the STM32F105 and STM32F107 interconnected series microcontrollers, STMicroelectronics had launched the STM32 basic series, enhanced series, USB basic series, and complementary series; the new series continues to use the 72MHz processing frequency of the enhanced series.
Memory includes 64KB to 256KB of flash memory and 20KB to 64KB of embedded SRAM. The new series adopts three packaging types: LQFP64, LQFP100, and LFBGA100, with different packages maintaining pin arrangement consistency. Combined with the design philosophy of the STM32 platform, developers can re-optimize features, memory, performance, and pin count through product selection to meet personalized application needs with minimal hardware changes.
STM32 Reset Circuit Design
The function of the reset circuit is to restore the system to its initial state. There are several types of reset methods for microcontrollers: power-on reset, system reset, and backup area reset.
Power-on Reset: This occurs when the system is powered on, powered off, or when the system returns from standby mode. The power-on reset can reset all registers except for those in the backup area.
System Reset: A system reset can be triggered by any of the following events:
1. Low level on the NRST pin (external reset)
2. Window watchdog timer expiration (WWDG reset)
3. Independent watchdog timer expiration (IWDG reset)
4. Software reset (SW reset)
5. Low-power management reset
The system reset can reset all registers except for the reset flag in the clock control register CRS and the registers in the backup area.
Backup Area Reset: For backup area reset, one method is to set the corresponding bit in the backup area control register during a software reset; another method occurs when both power and battery are lost and then powered back on.
Commonly used reset methods include two types: one is the low-level reset of the NRST pin, which is done by providing a low level to this pin through a reset circuit, allowing the system to complete the reset. The other is the well-known power-on reset. Although it is not used as frequently as the key reset circuit, it is still a common reset method. The circuit for the key reset is directly illustrated, and the explanations found online may have covered this circuit diagram extensively, so I won’t elaborate further.
Capacitance Charging Time Calculation: T = 1.1RC = 1.1 * 10000 * 0.0000001 = 0.0011s = 1.1ms
STM32 Core Reset and System Reset
Difference Between Core Reset and System Reset
The core referred to in this article is the processor core, namely the MPU (Microprocessor Unit). For example, the STM32F103 has a Cortex-M3 core.
The system here includes both the core and peripherals, which is the MCU (Microcontroller Unit). For the STM32F103, it is the Cortex-M3 core plus various peripheral interfaces.
Core Reset: Resets only the Cortex-M3 processor without resetting the registers of peripherals such as GPIO, TIM, USART, SPI, etc.
System Reset: Resets both the Cortex-M3 processor and the peripheral registers.
Therefore, the reset we commonly refer to generally refers to the system reset.
Source Code for Core Reset and System Reset Functions
This article uses the Cortex-M3 (STM32F103) as an example; other chips are similar.
Four reset functions have been written: Core Reset (C language), Core Reset (Assembly), System Reset (C language), and System Reset (Assembly):
void NVIC_CoreReset(void); // Core Reset (C language)
void NVIC_CoreReset_a(void); // Core Reset (Assembly)
void NVIC_SystemReset(void); // System Reset (C language)
void NVIC_SystemReset_a(void); // System Reset (Assembly)
The C language source code for NVIC_SystemReset is provided in the core_cm3.h file in the official ST library.
The Cortex-M3 allows for a software-triggered reset sequence for special debugging or maintenance. There are two methods to achieve self-reset in Cortex-M3.
The first method: Set the VECTRESET bit (bit offset: 0) in the NVIC application interrupt and reset control register (AIRCR).
NVIC_CoreReset Core Reset
This reset affects the entire Cortex-M3 processor, covering all corners except for the debugging logic, but does not affect any circuits external to the Cortex-M3 processor, so the on-chip peripherals and other circuits on the STM32 are unaffected.
The C language source code for the NVIC_CoreReset function is as follows:
staTIc __INLINE void NVIC_CoreReset(void)
{
__DSB();
// Set VECTRESET
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_VECTRESET_Msk);
__DSB();
while (1);
}
Assembly version of the function source code:
__asm void NVIC_CoreReset_a(void)
{
LDR R0, =0xE000ED0C
LDR R1, =0x05FA0001 // Set VECTRESET
STR R1, [R0]
deadloop_Core
B deadloop_Core
}
Core Reset main notes: SCB_AIRCR_VECTRESET_Msk and LDR R1, =0x05FA0001, this is the only difference from the system reset.
The second method: Set the SYSRESETREQ bit (bit offset: 2) in the NVIC application interrupt and reset control register (AIRCR).
NVIC_SysReset System Reset
The system reset sets the SYSRESETREQ bit in the same register. This reset will affect all circuits on the chip: it will cause the Cortex-M3 processor to assert the request line sent to the system reset generator. However, the system reset generator is not part of the Cortex-M3; it is implemented by the chip manufacturer, so the response to this reset varies across different chips. Therefore, readers need to carefully refer to the chip specifications to understand what the initial state of each peripheral and functional module will be when an internal chip reset occurs, or which functional modules are unaffected (for example, the STM32 series chips have a backup storage area that is treated specially).
In most cases, when the reset generator responds to SYSRESETREQ, it will also assert the system reset signal (SYSRESETn) of the Cortex-M3 processor. Typically, SYSRESETREQ should not reset the debugging logic.
One issue to note here: there is often a delay from when SYSRESETREQ is asserted to when the reset generator executes the reset command. During this delay, the processor can still respond to interrupt requests. However, our intention is often to stop execution at this point and not to do anything else. Therefore, it is best to set the FAULTMASK before issuing the reset request. This can be done using the following assembly statement: __disable_fault_irq();.
The C language source code for NVIC_SystemReset provided in core_cm3.h is as follows:
staTIc __INLINE void NVIC_SystemReset(void)
{
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
Assembly version of the function:
__asm void NVIC_SysReset_a(void)
{
LDR R0, =0xE000ED0C
LDR R1, =0x05FA0004
STR R1, [R0]
deadloop_Sys
B deadloop_Sys
}
Conclusion
Some systems allow resets but have special requirements for peripherals: for example, a certain IO state must not change due to a reset, or a certain timer counter must not change, etc. Example: System A controls the power of System B through an IO, and this IO must be high to turn on the power of System B.
During normal operation, System B will only shut down when it receives a shutdown command from System A (meaning it cannot be powered off). However, System A may require a reset during its operation.
If a conventional reset method is used at this time, it will reset the IO, which does not meet the requirements. If there were a method that only resets the core without resetting the peripherals, that would be ideal.
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