AI ASIC Tracking – September 5, 2025

2026 ASIC Shipment Volume and Value Forecast
Google TPU 2026 Forecast Continues to be Revised Upwards
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Within just three months, the upstream CoWoS “guaranteed capacity” has been revised from 1.2M → 1.5M → 1.8M → 2.0M units, and is currently negotiating towards 2.7-2.8M units, which is a 50% increase compared to the original forecast.
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Google TPU accounts for approximately 60% of the total ASIC value, making it the absolute leader.
Meta: The First 2nm ASIC “Olympus” Launches
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In the second half of 2027, two 2nm chips will be launched simultaneously:
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High-end Olympus (12 HBM3E, 2 compute dies) will continue to be outsourced to Broadcom;
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Low-end side-project (COT model, front-end self-research + back-end bidding) is currently selecting Marvell/MTK/Alchip/GUC.
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Although the side-project volume is less than Olympus, its ASP is high, making it very attractive to design service providers.
Other CSP Trends
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Amazon: Still a CoWoS Tier-2, if unable to secure released capacity from others, may downgrade Trainium 2.5 to Trainium 3.
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OpenAI: Maintains the plan for 136k units, with a ramp-up in Q4 2026 unchanged.
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Apple: Internal route conflicts make mass production difficult in 2026, timeline delayed.
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Oracle/ByteDance: ASICs may not be ready until 2027-2028, with end customers likely being large Chinese cloud providers.
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xAI: Currently has very low visibility, no forecast provided.
Supply Chain and Process Node Distribution (Document 2 Node Diagram)
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3nm becomes mainstream in 2026: Google TPU v7p/v8p, Meta MTIA-3, Microsoft Maia-200, Amazon Trainium-3, OpenAI v1, etc.
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2nm is positioned early: Microsoft Maia-300, Meta Olympus, Google TPU v8e/v9p, entering mass production in 2027.
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CoWoS/Advanced Packaging remains the biggest capacity bottleneck; Google is prioritized, while AWS/OpenAI and other Tier-2s face the risk of being squeezed.
Conclusion
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The global CSP ASIC market size in 2026 is estimated to be around $42-45 billion, with Google dominating over 60%, and still has room for upward revision.
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Broadcom is the biggest beneficiary of ASIC design services, followed by Marvell;Alchip/GUC have entered the second tier due to orders from Amazon and Microsoft.
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3nm/2nm and high-end specifications like 12-HBM are deeply binding ASIC design with advanced packaging, featuring high ASP and high entry barriers.
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If CoWoS capacity tightens further, Tier-2 customers (AWS, OpenAI) may see delays in ramp-up; Apple’s internal conflicts indicate that self-developed chips are not smooth sailing..