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Red Semiconductor announced the launch of a multifunctional intrinsic structured computing (VISC) architecture for RISC-V. VISC is an extension of RISC-V IP that accelerates complex algorithms and adds parallel processing to improve AI operations in edge computing.
James Lewis, CEO of Red Semiconductor.
One of the strong value points of RISC-V is the potential for customization within the standard. Red Semiconductor leverages this to develop a high-performance architecture that can be licensed. The VISC instruction set architecture (ISA) adds edge AI, autonomy, and cryptographic capabilities to the open-source RISC-V. The code is optimized for FPGA and ASIC SoCs.
What is VISC?
VISC is a vector processing engine built into RISC-V processor chips. It originates from the open-source Libre-SOC. Libra-SOC aims to bring complex algorithms, often reserved for GPUs, into microcontrollers and CPU-based small devices. Red Semiconductor built VISC on top of Libra-SOC and the open-source CPU RISC-V architecture. The result is a CPU core that is RISC-V compatible and has vector AI processing extensions.
Red Semiconductor claims that VISC outperforms other small systems/high computational demand processing devices while consuming less power. It enhances performance by using hardware components to deconstruct algorithms into blocks optimized for parallel processing.
Advantages of VISC
VISC RISC-V processors are said to improve the efficiency of algorithms typically used for artificial intelligence and machine learning, as well as other highly complex mathematical operations like cryptography and codecs, by up to 100 times. It relies on a single issue multiple execution architecture and memory-efficient 64 x 128 deep byte-accessible registers to reduce power consumption. The system breaks down algorithms into smaller parts that can be executed in parallel without the synchronization issues often encountered in parallel processing. By doing so, large computations can take less time and consume less power.
VISC in FPGA and ASIC
Developers have been adding CPU cores to FPGA and ASIC chips for some time now, with Arm cores being among the most popular. However, FPGA and ASIC developers relying on Arm are affected by the speed of Arm’s product releases. As RISC-V is open-source and adaptable, it has become a popular alternative for developers looking to accelerate the development of SoC products. With artificial intelligence sweeping the globe, FPGA and ASIC device developers are eager, which is where Red Semiconductor comes into play.
Founded in 2021, Red Semiconductor is following the RISC-V and AI trends. With support from the ChipStart UK incubator, the founders of Red Semiconductor saw a growing demand among FPGA and ASIC developers for edge AI computing and more flexible AI options. VISC is their answer.
Red Semiconductor and global computing challenges.
VISC brings accelerated AI capabilities to FPGA and ASICs that require RISC performance and flexibility. As an IP design, it can serve as a soft processor core added to FPGA configurations or as hard silicon in ASICs. As an enhancement to RISC-V, VISC brings optimized artificial intelligence and heavy mathematical computation capabilities to FPGA, ASIC, and SoC domains.
VISC in the Real World
If 2023 is the year of cloud-based generative artificial intelligence, then 2024 will be the year of edge artificial intelligence. However, this technology requires remote devices to provide more power. Cars, smartphones, medical devices, industrial controls, and other field products need to process, interpret, make decisions, and take actions without spending time routing data to or from the cloud.
VISC provides developers with the option to add highly AI-optimized RISC-V to their edge devices while remaining conservative on power consumption and cost budgets.
Original Text in English
https://www.allaboutcircuits.com/news/visc-new-coprocessing-riscv-architecture-ai-efficiency/
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