“ Over the past decade, RISC-V has transitioned in China from concept popularization to application flourishing. With continuous policy support, sustained investment in research, and active engagement from enterprises across the industry chain, China’s RISC-V ecosystem has gradually formed a panoramic map of “from laboratory to industrialization.” This article attempts to outline the core forces and distribution patterns of this ecosystem from three dimensions: “Policy—Research—Industry Chain”, and presents a quadrant diagram to show the positioning of industry chain enterprises in terms of computing power and application directions, providing a clear map for understanding the current development of RISC-V in China.”
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Government Support and Standardization (Top-Level Guidance)
Policies are no longer just point subsidies but are integrated advancements of “standards—conferences—alliances—scenarios,” aiming to create a “common foundation” for hardware and software that is verifiable, reusable, and mass-producible.
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Policy Trends: In March 2025, several ministries are expected to issue guiding opinions encouraging national applications of RISC-V, with the core intention being “to reduce dependence on external technologies through open-source ISA and accelerate industrial substitution and innovation diffusion.” This has been interpreted by various media and industry organizations as a signal of “systematic advancement from point pilot projects.”
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Industry Activities and Ecological Platforms: The RISC-V Summit China has established itself as an annual event (2025 in Shanghai Zhangjiang, with over 4000 participants), becoming a venue for the concentrated release of policies, research, and industrial achievements.
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Standards and Profiles: The RVA Profile (such as RVA23) aimed at the general software ecosystem has become the “minimum common standard” for chip/software collaboration, with domestic high-performance cores gradually aligning (e.g., XuanTie C930 is nominally compatible with the RVA family and supports extensions like Vector/Crypto/AIA).
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Openness and Governance: The government emphasizes embracing open-source standards (such as RISC-V and open-source OS), promoting open-source collaboration and talent cultivation through foundations/alliances and universities (e.g., CRVA, OpenAtom, etc.).
Universities and Research Institutes (Source of Innovation)
Universities/national research institutions drive innovation with a dual approach of “large scientific devices + open-source projects”: creating reusable IP/tools while also establishing methodologies as engineering standards and talent training pathways.
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Chinese Academy of Sciences System
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ICT “Xiangshan” Open-Source High-Performance CPU: Targeting server-like/high-performance scenarios, continuously iterating (Nanhua/Yanqi Lake/Kunming Lake), publicly stating in 2025 that it will achieve mass production breakthroughs; open-source repositories, papers, and toolchains evolve together, forming methodologies and community influence.
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Soft Institute PLCT Lab: Focused on collaboration among compilers, runtime, simulators, and distributions (LLVM/QEMU/various Linux distributions), has obtained RISC-V Ecosystem Lab certification, and is responsible for training and community collaboration (NixOS/RVV optimization, etc.).
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Tsinghua University System
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RIOS Lab (Tsinghua-Berkeley Shenzhen): Advocating the philosophy that “open architecture ecosystems should be free,” promoting hardware-software collaboration and educational ecosystems.
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Ventus GPGPU: An academic-level GPGPU research prototype aimed at RVV heterogeneous computing, covering compilation/verification/hardware collaboration, continuously recruiting community contributions.
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Zhejiang University System
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RVSC Hosting and Innovation Platform: In 2024, it will gather over 3000 offline participants and over a hundred exhibiting organizations in Hangzhou, forming a conference brand and results transformation channel for “research-industry connection.”
- Beijing Open Source Chip Research Institute (BOSC), established on December 6, 2021, is an innovation consortium initiated by the Beijing Municipal Government, the Chinese Academy of Sciences, and several leading domestic enterprises and research institutions. The mission of the institute is to build an open-source chip technology system, accelerate the development of the open-source chip ecosystem, particularly focusing on the technological research and industrial application of the RISC-V instruction set architecture.
Core Enterprises (Chip Design—Toolchain—Software Stack)
The industry has transitioned from “evaluation and verification” to the “product stratification + roadmap” stage: low-power MCUs (automotive/industrial)—mid-range edge SoCs (multimedia/storage/network)—high-core-count general/AI servers advancing simultaneously.
Chips and IP
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Alibaba Tsinghua Tongfang XuanTie: From the open-source high-performance core C910 to the C930 server-grade core, claiming 6-decode/16-stage pipeline, targeting AI-HPC/multi-core SoCs, and aligning with the RVA family and AIA/Vector/Crypto extensions; independent analysis of C910 microarchitecture and performance evaluation is also available.
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Chipcome Technology Nuclei: One of the first RISC-V processor IP manufacturers in mainland China, covering MCU to functional safety (ISO 26262) levels, with toolchain and compiler ecosystems aimed at automotive and industrial expansion.
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SOPHGO (SuanNeng):SG2042 64-core general RISC-V SoC has been mass-produced for servers/clusters, with a public roadmap including subsequent products; evaluations of its HPC performance have been conducted by both industry and academia.
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StarFive (Chipcome Ecosystem Partner):JH7110 has been mass-produced and used in motherboards/development boards and industrial collaborations (such as integration with VeriSilicon display IP); also promoting collaboration in the Hong Kong ecosystem and talent development.
Toolchain and Software Stack
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Compilers/Runtime/Distributions: PLCT continues to invest in LLVM, QEMU, and Linux distributions (including NixOS collaboration), forming a collaborative closed loop of “IP-features—compilation—verification—distribution.”
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Systems and Middleware: Domestic RTOS (such as the active RT-Thread community) are co-built with manufacturers/universities at Summit China; the popularization of the RVA Profile is introducing “application binary interface stability” into enterprise engineering discipline.
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Application Traction: AI/HPC, embedded systems, and automotive applications are the three main landing focuses—C930/SG2042/functional safety IP correspond to their respective tracks, forming a combined approach “from core to system.”
Conclusion
The advancement model of RISC-V in China is shifting from “substitution-driven” to a collaborative evolution of “standardization + open-source engineering methods + industrial roadmaps.” It is recommended that your subsequent chapters be organized according to “Instruction Set Standards—Toolchain—Core IP—Reference SoC—Landing Scenarios,” with each chapter providingannual metrics (RVA alignment, RVV support, functional safety levels, upstream integration status, mass production, and customer cases), ensuring that “annual comparisons are possible, and quarterly increments are traceable.”
Reference Links
https://www.electropages.com/2025/01/support-added-risc-v-ip-automotive-high-safety-and-security-applications
https://chipsandcheese.com/p/alibabat-heads-xuantie-c910
https://www.rioslab.org/
https://plctlab.org/ja/news/016
https://hic.zju.edu.cn/hicenglish/2024/0823/c82671a2954568/page.htm
https://discourse.nixos.org/t/plct-lab-intends-to-collaborate-on-risc-v-support
https://github.com/THU-DSP-LAB/
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