1. Registers
CM3 has general-purpose registers R0 to R15 and some special function registers.
For general-purpose registers R0 to R12, the initial reset values are unpredictable.
2. CM3 has a set of general-purpose registers from R0 to R15.
Note: Most 16-bit Thumb instructions can only access R0 to R7, while 32-bit Thumb-2 can access all registers.
3. Special Function Registers
3.1 Program Status Register Group (Application Program PSR + Interrupt PSR + Execution PSR)
3.2 Interrupt Mask Register Group: Used to control the enabling and disabling of exceptions.
3.3 Control Register: Used to define privilege levels and which stack pointer is currently in use.
4. Operating Modes and Privilege Levels:
There are two operating modes (processor modes): Handler mode and Thread mode (used to distinguish between the code for exception service routines and normal program code).
There are two privilege levels: Privileged level and User level (referring to the hardware-level memory access permissions).
Note: CM3 can use both privilege and user levels while running the main program (i.e., Thread mode); however, exception service routines (i.e., Handler mode) can only use the privileged level. Some access permissions will be prohibited when in Thread + User mode.
Distinguishing code into user and privileged levels is beneficial for program architecture stability; for example, if a user-level code encounters an issue, it will not become a bad apple, because user-level code is prohibited from operating on certain critical registers.
5. Exception Handling
5.1 CONTROL[0]=0;
5.2 CONTROL[0]=1;
CONTROL[0] can only be accessed at the privileged level. If access is needed at the user level, it must first trigger an SVC exception through the “System Service Call Instruction (SVC)”; then, in the service routine for that exception, CONTROL[0] can be modified.
6. Below is the transition of various operating modes.
7. Exceptions and Interrupts
There can be 11 system exceptions and up to 240 external interrupts (IRQ), depending on how many are used by the chip manufacturer.
As an enhancement of interrupt functionality, the NVIC also has a NMI input signal line, which is determined by the chip manufacturer, NMI (not masked interrupted).
8. Vector Table: When an exception is accepted by the CM3 core, the corresponding exception handler will execute, and the vector table is used to determine the entry address of the handler.
9. CM3’s dual stack: Main Stack (MSP) and Process Stack (PSP), controlled by CONTROL[1].
10. Reset Sequence:
First, retrieve the value of MSP from address 0X00, then retrieve the initial value of PC from address 0x04; the value at 0X04 is the reset vector, not a jump instruction.
Here, CM3 differs from ARM and microcontrollers. Previously, ARM always executed the first instruction from address 0X00, and the first instruction was usually a jump instruction.
11. An example of MSP and PC initialization.
