Understanding the Architecture of Arm Cortex-A53 Cache
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This article is authorized and reprinted from the WeChat public account Arm Selected. This article mainly shares the architecture interpretation of A53 cache.
1 A53 uses the classic big-LITTLE architecture
Below is an early classic big-LITTLE architecture diagram.
Figure 1
Figure 2
2 A53's cache configuration
L1 I-Cache
● Configurable: 8KB, 16KB, 32KB, or 64KB
● Cache line: 64 bytes
● 2-way set associative
●
