XILINX set_property BITSTREAM.CONFIG.CONFIGRATE
Cause In a new XILINX XCKU040 FPGA design, SPI supports X8 mode, and the BIT generation constraints are as follows: # the hardware support spix8, will boot faster from flash #set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] #set_property CONFIG_MODE SPIx8 [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property CONFIG_MODE SPIx4 [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property … Read more