This article elaborates on the core components and importance of the clock system in microcontrollers (MCUs). It points out that the performance and power consumption of an MCU fundamentally depend on its clock system. This system is based on a clock source (external crystal oscillator or internal RC oscillator) and distributes signals to various modules through a clock tree. To optimize power consumption, the industry commonly employs clock gating and frequency division techniques. Additionally, to address challenges such as power consumption and external interface synchronization, modern MCU designs often utilize multiple independent asynchronous clock domains instead of a single global synchronous clock. Therefore, proper clock configuration is key to ensuring stable system operation.
In most scenarios, a single clock source frequency cannot meet the different rate requirements of various internal modules of the MCU. The Phase-Locked Loop (PLL) can solve this problem; it can be viewed as a frequency synthesizer that can multiply or divide frequencies to generate different clock frequencies, such as converting 50MHz to 200MHz, provided there is a reliable ’50MHz’ as a reference.
If this reference is unstable, fluctuating between fast and slow, the 200MHz generated by the PLL will also be unstable. Just like building a tower, how high and beautiful the tower can be ultimately depends on how deep and stable the foundation is. The ‘foundation’ in the clock system is the clock source (Clock Source).
Whether we are using a solid rock-like pile (external crystal oscillator) or casually laying a layer of cement on sandy ground (internal RC oscillator) determines the upper limit of system stability. When working on projects, we need to balance cost and performance.
| Clock Source Type | Main Advantages | Main Disadvantages | Typical Applications |
|---|---|---|---|
| External Crystal (XTAL) | High precision, low temperature drift | Higher cost, occupies PCB space | High-speed communication, wireless RF |
| Internal RC Oscillator | No external cost | Low precision, susceptible to temperature and pressure variations | Low-speed, cost-sensitive applications |
Once we have selected the appropriate clock source, we have a stable and high-frequency main clock. The next question arises: how to drive signals to the hundreds of millions of transistors on the silicon chip with minimal delay and jitter? This requires high physical wiring standards, and this is also the core of the clock tree. The clock tree can provide an efficient distribution network to transmit signals to all corners of the MCU, ensuring that the clock signals received by all components have minimal delay and deviation.
When driving and distributing clock signals, some costs are unavoidable; that is, dynamic power consumption occurs during long-distance signal transmission, which also generates heat, making it one of the main bottlenecks limiting chip performance. The common practice in the industry is to manage power consumption using clock gating and clock division.
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Clock Gating: Turning off the clock for idle modules;
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Clock Division: Providing a reduced clock for low-speed peripherals.
The logic of the clock tree is clear; it primarily creates a perfect, globally synchronized system where all logic units strictly adhere to a single clock edge. Ideally, the entire chip should only have one synchronous domain driven by the clock tree.
However, the ideal state of ‘global synchronization’ faces three unavoidable challenges in reality:
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Power Consumption: Running the entire chip, including those modules that are in long-term sleep, at high-speed clock is a waste of power, and our costs do not allow for it.
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External Interfaces: When the chip communicates with external devices, the external device’s clock is almost impossible to fully synchronize with the chip’s internal clock.
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IP Reuse: Integrating third-party, pre-designed IP cores that come with their own clock designs.
Solving these problems is straightforward: integrate multiple asynchronous clocks within the chip. This means dividing the SoC into multiple areas, allowing each area to have its own clock, each doing its own thing without interference. Each of these areas driven by independent clocks is referred to as a clock domain.