FPGA Practical Operation Guide: SDRAM Instructions

Welcome FPGA engineers to join the official WeChat technical group.

Clickthe blue wordsto follow us, FPGA Home – the best and largest pure FPGA engineering community in China.

SDRAM is a commonly used device for caching data in embedded systems. The basic concepts are as follows (note the differences between several commonly used memories):

SDRAM (Synchronous Dynamic Random Access Memory) is a type of memory that requires a synchronous clock for operation. The sending of commands and the transmission of data are based on this clock. Dynamic refers to the need for constant refreshing of the storage array to prevent data loss, as SDRAM stores data using capacitors. As we know, capacitors discharge when left in a natural state, and if the charge runs out, it means the data in SDRAM will be lost. Therefore, SDRAM must be refreshed before the capacitor’s charge runs out. Random means that data can be read and written at specified addresses rather than in a linear sequence.

1. Precautions

Below are some easily misunderstood details that I summarized during my learning process. If you are unclear about some concepts, it is recommended to first study the basic concepts.

1.1 Burst Length

Burst transfer means that after specifying the row address, as long as the starting column address and burst length are specified, the memory will automatically perform read/write operations on the corresponding number of storage units without needing the controller to continuously provide column addresses.

• Reading and writing to SDRAM devices are burst-oriented, and the burst length (BL) is programmable.

• The burst length determines the maximum number of column positions that can be accessed for a given read/write command.

• Whether in sequential or interleaved burst types, the burst length can be 1, 2, 4, 8, or continuous. For sequential burst types, it is also applicable for continuous page bursts.

• Continuous page bursts are used together with the BURST TERMINATE command to generate arbitrary burst lengths.

• The reserved state should not be used as it may lead to unknown operations or mismatches with future versions. When a read or write command is submitted, a block equal to the burst length is effectively selected. All accesses to that burst occur within this block, meaning that when a boundary is encountered, the burst wraps within the block. When BL=2, this block is uniquely selected by A[8:1]; when BL=4, by A[8:2]; when BL=8, by A[8:3]. The remaining address bits are used to select the starting address within the block.

1.2 Auto Refresh (AR) and Self Refresh (SR)

Refresh operations are divided into two types: Auto Refresh (AR) and Self Refresh (SR). Regardless of the refresh method, there is no need for external row address information, as this is an internal automatic operation.

For AR, the SDRAM has an internal row address generator (also known as a refresh counter) that automatically generates row addresses in sequence. Since the refresh is for all storage cells in a row, there is no need for column addressing, meaning CAS is valid before RAS. Thus, AR is also known as CBR (CAS Before RAS) refresh. Since the refresh involves all L-Banks, all L-Banks stop working during the refresh process, and each refresh takes 9 clock cycles (PC133 standard), after which normal operation can resume, meaning that during these 9 clock cycles, all working commands can only wait and cannot execute. After 64ms, the same row is refreshed again, and this process continues in a cycle. Clearly, the refresh operation will affect the performance of SDRAM, but this is unavoidable and is the price paid for DRAM’s cost advantage over SRAM (static memory that retains data without needing refresh).

SR is mainly used for data retention in low power states during sleep mode, with the most famous application being STR (Suspend to RAM). When the AR command is issued, setting CKE to inactive enters SR mode, during which it no longer relies on the system clock but refreshes according to an internal clock. During SR, all external signals except CKE are invalid (no external refresh instruction is needed), and only reactivating CKE can exit self-refresh mode and enter normal operation.

2. Instructions

Taking the SDRAM chip IS42S16320D as an example, we will explain the implementation methods as detailed as possible. The relevant Verilog code will be provided later.

2.1 Timing

The timing diagram is shown below. During the operation, each command execution or data read/write must meet the corresponding timing requirements, so be careful.

To meet the setup time tCMS and hold time tCMH required for command latching, the SD_clk must be inverted or divided from clk. The system clock clk is 100MHz.

2.2 Refresh Time

The maximum time that the internal capacitors of SDRAM can retain data is 64ms, and we have 8K rows in one BANK, so 64ms/8k ≈ 7.8us. This means that to ensure that the data inside SDRAM is not lost, the maximum time interval between two refreshes must be 7.8us. Therefore, to give SDRAM more time for read or write operations and leave a buffer, we set the SDRAM refresh cycle to 7.7us.

From the timing perspective, if a refresh is needed during read/write, it should first enter PRECHARGE, then IDLE, and then refresh.

Therefore, we must ensure that refresh time + waiting time <= 7.8us. If reading, the waiting clock cycles are activation time (tRCD) + CAS Latency (tCL) + time to read a page + precharge time (tRP). If writing, the waiting clock cycles are activation time (tRCD) + time to write a page + precharge time (tRP).

In implementation, a combination of timed and manual control refresh can be used. A 7.7us timing counter continuously runs, and if it hasn’t counted to 7.7us and receives a refresh request signal, it begins to refresh and resets the counter. This way, after each read/write (the complete read/write time should meet the above requirements), a manual refresh can occur. If waiting for a long time, the counter can perform timed refreshes.

2.3 Page Operations (full page)

Generally, to achieve fast large data read/write, page operations can be adopted, i.e., setting the burst length to full page. In page operation mode, SDRAM must use the burst stop command to stop its operation. To take advantage of the flexibility and efficiency of page mode, it is necessary to control the number of bytes operated at one time by external input data. In other words, before reading or writing data, the external system must control a register by writing the number of bytes to be operated, and during the read/write operation, the SDRAM controller issues the burst stop command at the appropriate time based on the external provided byte count. This way, the read/write operations of SDRAM can flexibly adjust the byte count within the range of 1-256, enhancing versatility.

2.4 State Machine

The state diagram given in the IS42S16320D manual should be carefully understood for each state flow and transition conditions.

3. Detailed Operations

The operations of IS42S16320D mainly include power-on initialization, idle, read, write, refresh, and other states.

3.1 Initialization

After power-on, the chip has some fixed operations, which are clearly stated in the manual, as shown in the following image.

Mainly including the following operation steps, the chart represents the status of the operation pins.

• Power-on delay

After power-on, the chip has a delay of 100us (other RAMs mention 200us), during which command instructions are set to NOP or COMMAND INHIBIT. What about the state of CKE (whether it remains high or not)? It seems that it must remain high, as commands depend on the rising edge of clk, and to make clk valid, CKE must be set high?

• Precharge

After the power-on delay, precharge all banks. Precharging means closing the existing working row of the bank and preparing to open a new row.

• Auto Refresh

After charging is complete, wait for tRP Command Period (PRE to ACT) for a minimum of 15ns, then perform the first auto refresh, and after tRC Command Period (REF to REF / ACT to ACT) for a minimum of 60ns, perform the second auto refresh.

• Mode Register Configuration

After the second auto refresh, wait tRC (60ns) before setting the mode register. Note that the specific mode depends on the high/low levels of pins A9-A0. Refer to the diagram below.

• Initialization Complete

After the mode register is set, after tMRD Mode Register Program Time 14ns, the ACTIVE command can be given, meaning the row address is in working state.

As shown in the image below, the power-on initialization process for functional simulation is completed.

3.2 Row Activation

Before entering read/write from IDLE state, the row must be activated (ROW ACTIVE). After the row activation command is completed, a delay of tRCD Active Command To Read / Write Command Delay Time of 15ns is required before reading or writing can occur. For the same bank but different rows, activation requires at least 6 cycles of delay; for different banks and different rows, activation requires at least 2 cycles of delay, which can improve speed.

3.3 Write Data

The first data written aligns with the WRITE command. After writing the burst length, the input automatically becomes high impedance and stops receiving data. If writing a full page, if no burst terminate is given, it will start overwriting from the beginning.

If using full page write, when PRECHARGE is needed, time tDPL (14 ns, aligned with the rising edge of the last data) must be reserved. The writing process will be interrupted, and refreshing will start after the first timing (tRP). Generally, when writing is interrupted, DQM can be pulled high to block data input. The disadvantage of interrupting write operations with PRECHARGE is that it requires careful consideration of the appropriate timing to configure cmd and address. The advantage is that it can interrupt write operations at any time, regardless of whether it’s a fixed-length write operation or a full-page write operation.

Note: In the read or write commands, A10 controls whether to auto-precharge.

3.4 Read Data

During continuous reading, if a new command is added (write, read, precharge), the timing x must satisfy the CAS Latency – 1 cycle before the expected readout data arrives.

In the transition from read to write, the timing of the WRITE command should occur at the time of the last read data. However, in practical systems, to avoid conflicts during I/O switching between input and output states, the WRITE command is delayed by one cycle. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. Control DQM to avoid I/O conflicts, and DQM should be pulled high three cycles before the WRITE command. Note that DQM does not directly suppress output; it only suppresses the internal buffer, so when DQM is pulled high, the data from the previous buffer is still output. Before the WRITE command, DQM must be pulled low again; otherwise, the input will be invalid. (For example, if DQM was LOW during T4 in Figure RW2, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid.？？？)

4. Questions

• The execution process of periodic refreshes uses: after completing read/write in the same bank and same row, precharge first, then refresh twice. Can we just refresh without precharging????

• On the state machine, CBR automatically enters PRECHARGE, how is this explained?

Welcome communication engineers and FPGA engineers to follow the public account


The largest FPGA WeChat technical group in the country

Welcome everyone to join the national FPGA WeChat technical group, which has tens of thousands of engineers, a group of engineers who love technology. Here, FPGA engineers help each other, share with each other, and the technical atmosphere is strong! Hurry up and invite your friends to join!!

Press and hold with your finger to join the national FPGA technical group oh










FPGA Home Component City

Advantageous component services, if you have needs, please scan to contact the group owner: Jin Juan Email: [email protected] Welcome to recommend to procurement

ACTEL, AD part of the advantageous ordering (operating the full range):

XILINX, ALTERA advantageous spot or ordering (operating the full range):

(Above components are part of the models, for more models please consult group owner Jin Juan)

Service concept: FPGA Home Component Self-operated City aims to facilitate engineers to quickly and conveniently purchase component services. After years of dedicated service, our customer service is spread across large listed companies, military research units, and small and medium-sized enterprises. The biggest advantage is to emphasize the concept of service first, and achieve fast delivery and favorable prices!

Directly operated brands: Xilinx ALTERA ADI TI NXP ST E2V, Micron and more than a hundred component brands, especially good at components that are restricted from the US to China. We welcome engineer friends to recommend us to procurement or consult us directly! We will continue to provide the best service in the industry!











FPGA technical group official thanks to brands: Xilinx, intel (Altera), microsemi (Actel), LattIC e, Vantis, Quicklogic, Lucent, etc.