Who the hell told me what the hell M23 and M33 are?
How did it jump from single digits to double digits!
What happened to the previous ten brothers?
Don’t tell me it has anything to do with M3, will the next generation be called 2333333?
What comes will eventually come, so how can we simply and straightforwardly understand these two brand new processors? Here is a careless and simplified formula specially provided by a silly child:
Cortex-M23 =
Cortex-M0/M0 + Hardware Divider + Performance Improvement +
Dedicated Stack Overflow Hardware Detection +
Insignificant Actions in Instruction Set +
Security Extension (TrustZone for Armv8-M) +
Friendly Improvements to MPU Developer Model
Cortex-M33 =
Cortex-M3/M4 + Performance Improvement +
DedicatedStackOverflowHardware Detection +
Insignificant Actions in Instruction Set +
Security Extension (TrustZone for Armv8-M) +
Friendly Improvements toMPU Developer Model
-
Enhanced Version of Cortex-M0/M0+
According to official statements, Cortex-M23 implements the Baseline sub-architecture of Armv8-M, which we can understand as the “entry-level” product in mobile phones.
Note: Image from ARM official website
Cortex-M23 is also very direct in positioning, which is to add a security extension to Cortex-M0/M0+. Therefore, in fact, all binary codes compiled for Cortex-M0/M0+ can basically run on Cortex-M23/M33 “without modification” — unless your original code used the MPU. In addition, Cortex-M23 is surprisingly equipped with a hardware divider, which undoubtedly raises the “basic configuration” to a new level in the original market dominated by Cortex-M0 and Cortex-M0+.
In terms of instruction set, Cortex-M23 inherits from Armv6-M. In addition to supporting a series of instructions necessary for the “security extension”, this entry-level product also makes an “insignificant action” — that is, besides Cortex-M33, Cortex-M23 can also support “eXecute Only Memory, XOM” with very little cost.
What is dark code? It is similar to “dark matter” which can only be theoretically known to exist but is very difficult to detect —“Dark code” is a type of program that can only be executed (fetched) by the processor but cannot be read in any form (OPCODE) at all — this is commonly referred to as XO (eXecute-Only) code. “Dark code” is not implemented by the kernel, but it requires both the compiler and the kernel to work together to support it. This is because XOM is essentially a special area defined by the chip manufacturer in the address space — it can only be fetched by the processor for instruction execution, and cannot be accessed for normal data access.This requires that “dark code” cannot directly store any constants — they must be encoded into the instructions — existing as part of the instruction in the form of immediate numbers.
The instruction set of Armv6-M mostly consists of 16-bit Thumb instructions, and the binary length of the immediate numbers that can be used for encoding in 16-bit instructions is quite limited.Armv7-M introduced the 32-bit Thumb2 instruction set, greatly enhancing the ability to carry immediate numbers in instructions.To bring this capability into the Baseline instruction set of Armv8-M, the instructions MOVT and MOVW, which can carry 32-bit immediate numbers “high and low 16 bits” respectively, were specially added to the instruction set used by Cortex-M23. Considering the strong information security of Armv8-M, it’s easy to imagine how significant “dark instructions” are for protecting firmware.
2. Enhanced Version of Cortex-M3/M4
Compared to Cortex-M3/M4, the performance improvement of Cortex-M33 is not surprising, so it’s not worth mentioning. It’s worth noting that the Cortex-M7 from the city can still “outperform other Cortex-Ms by a mile” — the difference between a 6-stage pipeline and a 3-stage pipeline is not something that can be compared to the gap between a “three-cylinder Xiaoli and a six-cylinder BMW”! (Serious face).
Note: Image from ARM official website
3. ARMv8-M is a good student who corrects his mistakes
I don’t know how many people have actually used Armv7-M, which is the MPU of Cortex-M3/M4 — simply put, it’s a system-level peripheral that modifies memory attributes based on regions. The original design was simple, one region, give it a size (Size), give it a base address (Base Address), then give it an attribute (Memory Attribute), enable it, and it works, very simple, very happy. However, due to the optimization of the core area, a limitation was artificially added to the setting of the region address range:
The base address must be aligned with its size, and the size must be a power of 2 (and must be greater than 4).
So what did Armv8-M do? It corrected this painful setting, namely: The setting of the region has evolved from “base address + size” to “start address + end address”, apart from the requirement that both addresses must be multiples of 32 bytes, there are no more perverse limitations such as “the base address must be a multiple of the region size”. Don’t you suddenly feel enlightened, don’t you suddenly discover a treasure? The MPU suddenly became fun.
4. How to Simply Understand Security Extensions (Trust Zone for ARMv8-M)?
Please listen to the next episode.
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