Three Levels of Chip Integration

Source: SiP and Cash Packaging Technology

Original Author: Suny Li

Introduction

Integration refers to the process of bringing together different functional units to achieve specific functions, often associated with human activities. Terms like integrated circuit and system integration are commonly used.

In this article, we will analyze modern electronic integration technology from two aspects: Level and Step.

Integration

Levels of Integration

Electronic system integration is mainly divided into three levels: integration on the chip, integration within the package, and PCB-level integration, as shown in the figure below:

The basic unit of integration on the chip is the transistor, which we refer to as the Function Cell. A large number of Function Cells integrated together form the chip.

The basic unit of integration within the package is the bare chip or small chiplet completed in the previous step, referred to as the Function Unit. These Function Units are integrated within the package to form a SiP.

The basic unit of integration on the PCB is the package or SiP completed in the previous step, referred to as the MicroSystem. These MicroSystems are integrated on the PCB to form larger-scale systems.

It can be seen that the levels of integration proceed step by step, with each level’s function continuously improving based on the previous level, and the scale constantly expanding.

By the time we reach the PCB level, the electronic system’s functions are already quite complete, and the scale is expanded to a point suitable for human manipulation, along with other components, forming the most commonly used system—Common System, such as the mobile phones or computers we interact with daily.

Integration on the Chip

The transistors on the chip are called Function Cells because they are the smallest indivisible functional units.

The number of Function Cells also serves as an important indicator of the system’s advancement. The human body has approximately 40-60 trillion cells; for a system to be truly intelligent like a human, it may need to contain a similar order of magnitude of Function Cells.

To integrate more Function Cells, transistors can only become smaller and smaller. Today’s transistor sizes may be a billionth of the size of the first transistor invented, while their basic functions remain unchanged.

Integration on the chip requires first manufacturing Function Cells and integrating them together. How are these transistors, which serve as Function Cells, manufactured and integrated? From a minimalist perspective, we need to understand three types of materials and three types of processes.

Conductors, Semiconductors, Insulators

Although there are many materials on the chip, the materials used in modern integrated circuits can almost exhaust the periodic table of elements. All materials can be divided into three categories: conductors, semiconductors, and insulators.

Conductors are responsible for transmitting electrons, insulators are responsible for isolating electrons, and the most important is the semiconductor, as it is variable. It can sometimes act as a conductor (on) allowing electrons to pass through, and sometimes as an insulator (off) blocking electron flow. Furthermore, this change is controllable by designing special structures and applying current or voltage.

In conductors, the conduction band overlaps with the valence band, where there is no forbidden band, making it easy for electrons to move and form current under an external electric field; in semiconductors, a small portion of electrons can jump to the conduction band and form current under an external electric field; in insulators, electrons cannot cross the forbidden band, thus cannot form current.

Three Levels of Chip Integration

Processing Technology, Reduction Technology, Pattern Transfer

There are many processes for manufacturing chips, with the process flow to complete a chip manufacturing reaching over a thousand types. These processes can be classified into three categories: processing technology, reduction technology, and pattern transfer.

Processing Technology simply refers to adding materials on a substrate, for example, ion implantation, sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., can be classified as processing technology.

Reduction Technology is simply the removal of materials, such as etching, chemical mechanical polishing (CMP), wafer flattening, etc., can be classified as reduction technology.

Pattern Transfer is the most numerous and difficult among the three types of processes because each step of processing technology or reduction technology is generally based on pattern transfer. Pattern transfer involves transferring the designed patterns onto the wafer, involving masks, photolithography, and photoresist.

Pattern transfer is also a transfer of human thought and wisdom.

Each step of processing technology or reduction technology requires pattern transfer before and after to create specific patterns on the chip.

These patterns are stacked in multiple layers, combining the three types of materials: semiconductors, conductors, and insulators to form specific three-dimensional structures, creating Function Cells on the wafer plane, achieving the corresponding functions.

Three types of materials + Three types of processes can create such complex chips, which indeed echoes the ancient saying, “One gives birth to two, two gives birth to three, and three gives birth to all things.”

After thousands of processes, the product integrated on the chip is the wafer, which, after being cut, forms chips or chiplets, preparing for the next level of integration.

Three Levels of Chip Integration

Integration within the Package

Not all chips or chiplets need to be integrated within the package; a single chip can also be directly packaged and applied on the PCB. However, as Moore’s Law gradually becomes less effective, integration within the package is receiving increasing attention. Concepts such as SiP, advanced packaging, chiplet, heterogeneous integration, 2.5D, and 3D are becoming the focus of the industry, and integration within the package has finally ushered in its spring.

Three Levels of Chip Integration

Integration within the package does not utilize the characteristics of semiconductors, so the materials used for integration within the package are mainly divided into two categories: conductors and insulators. The main purpose of integration is to electrically connect the chip or chiplet completed in the previous layer (integration on the chip) within the package, forming a MicroSystem.

The initial packages were all single-chip, without the concept of integration. The main functions of traditional single-chip packaging are: chip protection, scale amplification, electrical connections.

Multi-chip packaging represented by SiP adds three more functions based on traditional packaging: increased functional density, shortened interconnection length, and system reconstruction.

Integration within the package alleviates the pressure of integration on the chip, thus being regarded as a miraculous weapon to delay the end of Moore’s Law.

Integration within the package is less challenging than integration on the chip because it does not require the manufacture of Function Cells (transistors) but merely involves assembling Function Units (chiplets).

Another feature of integration within the package is its high flexibility, which can be divided into five integration dimensions: 2D, 2D+, 2.5D, 3D, and 4D (see: The Scale and Dimension of Integration).

The result of integration within the package is the formation of functional units represented by SiP and advanced packaging, which we can refer to as MicroSystems.

Three Levels of Chip Integration

Integration on the PCB

From the history of electronic integration, PCB integration should be the earliest to appear. The emergence of PCBs predates packaging by 11 years and integrated circuits by 22 years.

Before the advent of PCBs, components were directly connected with wires, which not only looked messy but also made it difficult to increase integration density.

Although the PCB has the longest history compared to integrated circuits and packaging, its development in integration technology has been relatively slow due to constraints from packaging size and pin density. It has evolved from single-sided boards to double-sided boards and multilayer boards, with assembly technology evolving from through-hole mounting to surface mount technology (SMT), with assembly density increasing.

Today, PCBs mostly have components mounted on both sides, with layer counts reaching dozens. High-density HDI boards, rigid-flex boards, microwave circuit boards, embedded device boards, etc., are widely used.

Similar to integration within the package, PCB integration does not utilize the characteristics of semiconductors; thus, the materials used are mainly divided into two categories: conductors and insulators. The main purpose of integration is to electrically connect the MicroSystem modules completed in the previous layer (integration within the package) and, along with other components, form Common Systems, such as the mobile phones and computers we commonly use.

Three Levels of Chip Integration

Integration

Steps of Integration

We have discussed the three levels of integration in electronic systems: integration on the chip, integration within the package, and PCB-level integration. Each level of integration is divided into different steps.

Steps of Integration on the Chip

Integration on the chip is mainly divided into two major steps: device manufacturing and metal interconnection, also known as front-end process (FEOL) and back-end process (BEOL).

Device Manufacturing (Front-end Process)

Device manufacturing involves using processes such as photolithography, etching, ion implantation, sputtering, chemical vapor deposition, physical vapor deposition, chemical mechanical polishing, wafer flattening, etc., to create transistors, resistors, capacitors, diodes, and other components, which we refer to as Function Cells on a single crystal silicon wafer. The current 5nm process can manufacture over 100 million transistors in an area of 1mm².

The manufacturing process of transistors mainly includes isolation, gate structure, source-drain, and contact hole formation, generally referred to as the front-end process (FEOL, Front End of Line).

Single crystal silicon can form various doping concentrations such as N, N+, N-, P, P+, P- through ion implantation, while polysilicon is used as a gate or resistor.

The following image shows a photograph of a FinFET transistor under a microscope, where the higher white beam is the gate G, the lower beam is the Fin, approximately 0.67 times the width of the gate, with the source S and drain D located on both sides of the gate.

Metal Interconnection (Back-end Process)

After the transistor layer is manufactured, tungsten or other metals are used to create contact holes connecting the transistors and the first-level wiring, followed by multi-layer metal wiring and vias for electrical interconnection. Earlier chips used aluminum wiring, while modern chips predominantly use copper wiring.

The manufacturing of multi-layer metal wiring used to connect transistors and other components mainly includes dielectric deposition between interconnect lines, metal line formation, and pad formation, generally referred to as the back-end process (BEOL, Back End of Line).

Conductors used in metal interconnection include tungsten, copper, aluminum, etc., while insulators include silicon oxide, silicon nitride, high-k dielectrics, low-k dielectrics, polyimide, etc.

The following image shows a photograph of the metal interconnect lines on a chip under a microscope, illustrating the multi-layer wiring structure, with current processes supporting over 10 layers of metal wiring.

Three Levels of Chip Integration

The more advanced the integrated circuit process is, the smaller the structural dimensions become, leading to various effects emerging. To address these effects and manufacture functional transistors, the variety of elements used has increased, almost exhausting the periodic table of elements.

The following diagram illustrates the structural schematic of the front-end process (FEOL) and back-end process (BEOL). First, transistors are manufactured on a silicon substrate, then connected through metal interconnections and brought out to the chip’s PAD.

Three Levels of Chip Integration

Steps of Integration within the Package

Earlier packaging was relatively simple, mainly serving the functions of chip protection, scale amplification, and electrical interconnection. Its schematic diagram is roughly as follows, connecting the chip’s PAD to the package substrate or lead frame through bond wires, and then to external pins. Based on the arrangement of the pins, it can be divided into various packaging forms such as BGA, CGA, QFP, LCC, SOP, DIP, etc.

Three Levels of Chip Integration

Traditional packaging, due to its relatively simple internal structure, connects the chip’s pins using bond wires to a lead frame or substrate, while the external pin arrangements are diverse. Therefore, when discussing packaging, people often focus on its various external forms. Hence, we say: traditional packaging emphasizes the external rather than the internal.

However, with the advent of SiP and advanced packaging, this situation has changed dramatically. SiP and advanced packaging have gradually unified their external packaging forms to more pin arrangements and higher interconnection densities such as BGA and CGA, while the internal structure has become increasingly complex due to integrated functions. People’s focus on packaging has gradually shifted from external forms to internal structures. Therefore, we say: advanced packaging emphasizes the internal rather than the external.

To improve functional density within the package, it is necessary to integrate more functional units, and the traditional bond wire connection method can no longer meet the requirements. Various advanced packaging technologies have been invented, and we will take a look at some of the most typical technologies.

RDL and TSV Production on the Chip

On the chip surface, wiring is performed, and through the Redistribution Layer (RDL), the PAD is connected to a more relaxed position and bumps are created, which we refer to as the extension of the XY plane.

Then, through the bumps, the chip can be directly mounted onto the substrate. This process is known as Flip Chip, and as you can see in the image below, you will understand why it is called inverted.

The Flip Chip process emerged in the 1960s, contemporaneously with bond wires, and has a long history; I generally do not refer to it as advanced packaging.

Since Flip Chip cannot stack, it cannot extend in the Z-axis. Therefore, people invented a through-hole technology that penetrates the entire chip body, known as TSV (Through Silicon Via) technology.

TSV has many technical challenges that need to be overcome. I believe the most crucial issues are the selection of TSV positions and the reduction of hole diameters.

Because TSV needs to penetrate the entire chip body, poor position selection can damage internal circuit connections and transistors, making position selection crucial. Reducing hole diameters is also important to minimize space on the chip. After all, an area of 1mm² can accommodate over 100 million transistors; if not handled well, several hundred million could be lost at once.

However, the development of TSV technology is becoming increasingly powerful, with claims that up to one million TSVs can be etched in an area of 1mm², fully meeting the needs for high-density interconnections.

The following image illustrates the schematic of TSV on the chip, which connects the upper and lower surfaces of the chip through metal conductors, preparing for chip stacking.

Three Levels of Chip Integration

Creating TSV on the chip is extremely challenging, and only leading foundries can accomplish this. This type of TSV is usually referred to as 3D TSV.

To further enhance integration density, people have also invented TSV production on silicon substrates called 2.5D TSV.

RDL and TSV Production on the Interposer

Interposer, known as a silicon interposer, can provide higher interconnection density than ordinary substrates.

The following image shows a typical silicon interposer, with three metal layers on top, two metal layers on the bottom, and connections through silicon vias, which we call a 3+2 structure.

Three Levels of Chip Integration

TSVs on the interposer are usually larger and less dense than those on the chip, and are easier to manufacture. Currently, OSAT packaging factories can process this type of 2.5D TSV.

Once the interposer is manufactured, we can mount chips or chiplets onto the silicon interposer.

The following image shows that, due to the structure containing both 3D TSV and 2.5D TSV, we refer to it as advanced packaging of 2.5D+3D.

Manufacturing Interconnection Lines on the Substrate

Next, we also need to manufacture the packaging substrate. The materials for packaging substrates vary widely and can be classified into organic substrates and ceramic substrates.

Organic substrates are primarily made from organic resin and glass fiber cloth, with copper foil usually serving as the conductor. Common organic resins include epoxy resin (FR4), BT resin (bismaleimide triazine resin), PPE resin (polyphenylene ether resin), and PI resin (polyimide resin).

Ceramic substrates generally have better mechanical and thermal properties than organic substrates, typically including HTCC, LTCC, and aluminum nitride ceramic substrates.

The following image illustrates a typical organic substrate structure, with the middle four layers manufactured using the laminate method and the two outer layers produced using the buildup method, referred to as a 2+4+2 structure.

Three Levels of Chip Integration

Packaging substrates generally have devices mounted on the top and connect to the PCB through BGA at the bottom.

Device Assembly and Packaging

Next, we assemble the chiplets, interposers, and substrates together and apply advanced packaging processes to form a complete advanced package.

Three Levels of Chip Integration

The result of integration within the package possesses the functionality of a system and is compact in size; we can refer to it as SiP or MicroSystem.

Steps of Integration on the PCB

After integration is completed within the package, the size is still not large enough, and some discrete components, such as large capacitors and transformers, cannot be integrated into the chip package. Therefore, for electronic products, PCBs remain indispensable.

Manufacturing PCB Interconnection Lines

The manufacturing process of PCBs is similar to that of organic substrates, with wiring density not as high as organic substrates and a relatively simple structure.

PCBs mainly use through-hole structures; although high-density HDI boards also use blind and buried hole structures, through-holes are widely used in PCBs due to their simple structure and low cost.

The following image shows a 6-layer through-hole structure PCB, which can fix devices and provide electrical interconnections.

Component Assembly on the PCB

After the PCB is processed, it is necessary to assemble the packaged components onto the PCB, as shown in the image below, and connect to external plugs and devices through the PCB.

Three Levels of Chip Integration

Overall Diagram from Transistor to PCB

Below, we present an overall diagram from transistor (Transistor) to PCB, as shown below:

Three Levels of Chip Integration

(It is recommended that readers save this diagram, as it may be the first diagram in the industry illustrating the complete integration from transistor to PCB, hand-drawn by Suny Li. As this is a schematic diagram, it is not drawn to scale; in reality, the size expands by about 1,000,000 times from transistor to PCB.)

After transistors (NMOS or PMOS) are manufactured on the silicon substrate, they connect to the chip’s metal wiring through contact holes, then to the chip’s Pad, followed by RDL to 3D TSV, then uBump to RDL on the silicon interposer and 2.5D TSV, and finally to the packaging substrate through bumps, connecting to the PCB through wiring and vias.

From transistor to PCB, the complete five-level signal path is as follows:

Transistor→Contact→Copper→Pad→RDL¹→3D TSV→uBump→RDL²→2.5D TSV→Bump→Trace¹→Via¹→BGA→Trace²→Via²→PCB

On integrated circuit chips, humans have achieved functional creation through transistors, realized functional reconstruction and scale amplification on SiP or advanced packaging, and further carried out functional reconstruction and scale amplification on PCBs.

From transistor to PCB, the scale has expanded by a million times, matching the scale of human beings.

Ultimately, PCBs and other components are organically combined to become mobile phones that can be operated anytime and anywhere in the hands of modern people, and computers that are almost indispensable in work.

Editor: Lu Dingci

Three Levels of Chip Integration

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