RISC-V features high customizability, modularity, and diverse scenarios, bringing a series of advantages such as efficiency, flexibility, openness, and ease of collaboration to the computing industry. However, it also presents new challenges for chip verification and debugging. At the recently held Fifth RISC-V China Summit (hereinafter referred to as “the Summit”), how to enhance the development, verification, and debugging efficiency of RISC-V processors from the perspective of IP, EDA, and other design tools to fully leverage the advantages of the RISC-V instruction set became a focal point of industry concern.New Verification Methodology: Improving RISC-V Processor Verification Efficiency and QualitySimulation verification is a necessary step to ensure that the chip meets design goals and functions correctly, directly affecting the success rate of chip design. At the Summit exhibition area, reporters saw prototype verification platforms at booths of EDA companies such as SiFive and Chipone. According to staff from SiFive, based on FPGA prototype verification platforms and operating systems, RISC-V design companies can implement and simulate their written code through FPGA, and then carry out functional development and debugging. After completing this process, they can conduct customer demonstrations. “The benefits are twofold: first, it gives customers confidence; second, customers can integrate this complete environment, comparable to that after tape-out, into their systems for further development.”
SiFive Prototype Verification PlatformCurrently, the commonly used simulation framework for RISC-V processors is co-simulation verification, which involves simulating the design under test (DUT) alongside a reference model (REF). For each instruction executed by the DUT, the REF also executes an instruction, comparing the results of both executions to check for consistency.However, the technological trends of RISC-V are posing challenges to co-simulation verification. Firstly, the complexity of the RISC-V instruction set is rapidly expanding. For example, RVA23 has 33 mandatory extensions and an 830-page instruction set manual, which has doubled since 2019, and different RISC-V extensions have varying verification requirements, increasing the difficulty of verification. Secondly, the circuit simulation speed of processors is slowing down. Especially for software simulation, its speed significantly decreases as the processor scale increases.
Increased Complexity of the RISC-V Instruction Set
To improve chip verification quality and efficiency, the industry is turning to hardware simulation platforms based on Emulators and FPGAs, characterized by deploying the REF in the host environment, focusing on communication between hardware and software (RTL-Host), and using connection methods such as PCIe, Ethernet, and InfiniBand to transfer information between software (host side) and hardware (RTL side), achieving orders of magnitude acceleration in circuit simulation. For instance, the DiffTest framework maintained by the Xiangshan team has already supported hardware simulation acceleration.However, the Xiangshan team found that the communication overhead brought by the RTL-Host architecture limited the acceleration effect of DiffTest for complex processors like Xiangshan. To address this bottleneck, the Xiangshan team proposed the SVM (Synthesizable Verification Method), mapping the entire REF onto FPGA or Emulator, allowing communication between REF and DUT to be completed on-chip, thus avoiding communication overhead.However, building the SVM architecture also faces some challenges. In response, the Xiangshan team has conducted a series of technical and model innovations.Firstly, how to ensure the circuit code implementation of the REF. REF is usually a software instruction set simulator, and how to implement it in hardware description is still a blank. The Xiangshan team adopted semantic code migration technology, constructing an instruction operation tree to transform the basic semantics of Spike into the semantics of REF or RTL, supporting automatic migration of semantic information such as instruction functionality, control and status registers (CSR), and constants.Secondly, how to improve the execution efficiency of the hardware REF. The Xiangshan team proposed a hardware reference model (SRef) design: when the DUT submits N instructions, SRef executes N instructions and compares the results. At the same time, by employing a fully pipelined and non-blocking workflow, it eliminates control dependencies between RISC-V instructions.Thirdly, how to enhance the debuggability of the SVM framework. The Xiangshan team proposed a synthesizable debugging technology that converts the REF into an independently executable general-purpose CPU when the CPU encounters an error. This means that the REF can act as a CPU to read the on-chip extractor, determining which hardware assertion has failed, thus aiding in debugging.As the Xiangshan processor iterates to the third-generation architecture “Kunming Lake,” the number of cores has increased to 16, and a system-level SoC architecture aimed at high-performance computing scenarios has been constructed, further increasing the complexity of the CPU system, necessitating large-scale FPGA platforms and automated toolchains. Regarding the large-scale cascading FPGA system verification of the Xiangshan Kunming Lake 16-core CPU, the Xiangshan team has collaborated with EDA company Hejian Technology.
Verification Challenges of the Kunming Lake ProcessorAccording to Cao Mengxia, market director of Hejian Technology’s verification product line, building a large-scale FPGA system has three difficulties. Firstly, how to partition large-scale designs across different FPGAs, a problem that has troubled the industry for decades; secondly, how to ensure functional correctness after partitioning; and thirdly, how to establish accurate timing models.To address these challenges, Hejian Technology and the Xiangshan team have established a systematic multi-core processor FPGA verification methodology, including design migration and adaptation, maximizing the balance between compilation iteration efficiency and resource optimization, progressive startup strategies, and hardware-software collaborative debugging techniques.Based on this methodology, the two parties achieved four outcomes. Firstly, an automated compilation process. Besides necessary porting, critical tasks such as clock conversion, automatic partitioning, and TDM IP binding can be handled by EDA tools, allowing users to focus their most valuable time on the project itself. Secondly, performance targets were met, with the CPU main clock stably running at 10.2 MHz in the complete version of the 16-core system. Thirdly, a complete, untrimmed, bootable OS 16-core high-performance Kunming Lake RISC-V processor system was successfully run on the FPGA prototype verification platform. Fourthly, compared to traditional methods, overall verification efficiency improved by about 40%, significantly shortening the time to market for the product.In the future, both parties hope that EDA companies will collaboratively promote the standardization of RISC-V verification methodologies. Li Xianfei, a senior engineer at the Beijing Open Source Chip Research Institute (hereinafter referred to as “Kai Xin Yuan”), expressed hope that EDA vendors can develop more features supporting verification scenarios beyond CPU cores, including dynamic power verification and low-power verification. At the same time, Kai Xin Yuan hopes to work with EDA vendors to build a toolchain, including a hybrid verification model of Emulator and UVHS (prototype verification); in multi-core verification methodologies, to construct a verification methodology for memory consistency protocols, exploring a tracking framework for cross-core events. Additionally, based on new solutions, technologies, and methods provided by EDA vendors, they aim to explore applications related to the Wenyu River NOC, develop CPU Tracer-like debugging tools based on Emulators, and enhance power-performance joint analysis capabilities to provide a more comprehensive evaluation dimension for SoC design.More Refined Toolchains: Unlocking the Customizable and Scalable Advantages of RISC-VCustomizability and scalability are inherent advantages of RISC-V, but to enable developers to efficiently and conveniently create customized instructions that can run on CPUs, the toolchain still needs to provide support at a finer granularity.In a presentation, Andes Technology introduced its Andes ACE framework and AndesCycle simulation platform, which help accelerate the development and verification process of RISC-V custom instructions. According to Andes software engineer Yan Jingzhe, developers can submit ACE definition files and simplified Verilog files to the ACE framework’s COPILOT code generator to obtain the necessary extension files such as C language programming auxiliary function interfaces, assemblers, and OpenOCD debugging tools. COPILOT will also automatically generate Verilog code for control logic (ACE engine) and instruction modules, which developers can integrate into existing AndesCore processor architectures to obtain customized CPU instructions. Subsequently, developers can use the AndesCycle simulator to perform performance analysis and debugging of the instructions, thereby accelerating the development of custom instructions.ASIC (Application-Specific Integrated Circuit) chips based on the RISC-V instruction set are seen as an important opportunity for innovation in AI chip architecture. Research from the Wilson Research Group indicates that, on average, 50% of the time in ASIC projects is spent on verification, with projects that have the shortest verification times typically reusing pre-verified IP modules. Conversely, projects that take longer for verification often involve a large number of newly developed IP modules.To reduce the IP verification costs for RISC-V companies, the Siemens EDA team introduced an end-to-end RISC-V debugging and tracing solution called Ultra Sight-V, which includes operational control at the hardware IP level, efficient tracing, efficient debugging IP, pre-verified and mass production-verified IP, UVM (Universal Verification Methodology) verification environments, system scalability, and interfaces such as USB, JTAG, and AXI, along with a host software suite and user environments compatible with third-party tools. In debugging RISC-V core IP hardware, the Siemens team provided efficient tracing (E-Trace) for RISC-V instructions, capable of highly compressing the instruction trace. After enabling the scalable features of RISC-V tracing, the compression rate—i.e., the bits per instruction (BPI) required to record a test benchmark program—decreased by 40%. This means that using E-Trace for tracing consumes less bandwidth over the same time, allowing for longer error tracing within the same storage space and bandwidth.With the rapid development of the RISC-V ecosystem, the demand for SoC system modeling is increasing. Current mainstream RISC-V simulation tools include QEMU, Spike, and Gem5, each with different modeling advantages; for instance, QEMU has strong runtime performance, Spike is easier to develop, and Gem5 offers high simulation accuracy and compatibility with SystemC TLM. However, there are also some pain points. Firstly, the accuracy of QEMU and Spike is only at the functional level, and their accuracy needs to be improved to Near-Cycle level to support the extension of tools such as Profiling (performance analysis). Secondly, QEMU and Spike do not support SystemC TLM-2.0—standardized interfaces abstracting transaction-level communication, enabling plug-and-play compatibility of different vendors’ RISC-V models on the same virtual platform, facilitating integration into third-party VPs. Thirdly, the software interface of the models is not user-friendly, lacking sufficient convenience for integrating custom instructions.
Modeling Characteristics of Various Simulation ToolsTo address these pain points, Chiplet Technology has built the Nuclei Model. According to modeling engineer Xu Zitai, the Nuclei Model establishes a Timing Model based on ISS, achieving Near Cycle modeling accuracy for RISC-V SoC systems. After constructing the timing model, profiling is also required. The Nuclei Model has two profiling methods: one involves decoding instructions, outputting the program counter (PC) and cycle count to the profiling processing unit, and then presenting CPU usage through performance analysis tools like Gprof to analyze performance bottlenecks. The other method uses flame graphs, combining the advantages of Flame Chart and Flame Graph to achieve visualization features with time axis attributes, call stack relationships, and multi-threaded applications. After locating hotspot functions based on profiling, custom instructions can be quickly optimized in algorithm programs.To further leverage RISC-V’s open advantage of “any user can freely access the RISC-V instruction set,” the University of the Chinese Academy of Sciences launched the “One Chip Per Person” open-source processor chip teaching and tape-out practice project in 2019, allowing students to graduate with their designed processor chips. Xie Biwei, an associate researcher at the Institute of Computing Technology, Chinese Academy of Sciences, stated at the summit that the value of RISC-V lies in the ability for everyone to customize their chips, and achieving this goal requires open-source EDA.“The role of open-source EDA is akin to that of open-source compilers like GCC in the open-source software ecosystem,” Xie Biwei stated. The open-source chip ecosystem team he is part of has launched the ECOS Studio open-source chip design solution, promoting the open-sourcing of EDA tools and toolchains, and constructing SoC and backend learning processes and materials based on open-source EDA toolchains. It is reported that this solution has officially opened for internal testing at the “One Chip Per Person” summer presentation in July this year.
Follow China Electronics NewsFollow the Author of This Article
Further Reading:“Domestic EDA Tool Reputation Ranking” collection activity is about to close!EDA Companies’ “Voices”: Embracing a Healthy Industrial EcosystemAuthor丨Zhang XinyiEditor丨Qiu JiangyongArt Editor丨MariaSupervisor丨Zhao Chen
Click “View” to Stay Connected