Special Issue on Emerging Computing Chip Design Research
With the rapid development of information technology, artificial intelligence, big data, cloud computing, and the Internet of Things, the global demand for computing performance, energy efficiency, and intelligence continues to rise. Traditional chip architectures struggle to meet the requirements for high performance, low power consumption, and high concurrency in the face of complex, massive, and diverse data processing tasks. At the same time, as Moore’s Law slows down and the benefits of process miniaturization gradually diminish, the path of relying on traditional process technologies to drive performance improvements faces significant challenges. There is an urgent need to explore new architectures and design methods to break through performance bottlenecks and achieve continuous evolution and innovative development. Emerging computing chip design, as a key technological route to break the limitations of traditional architectures and enhance overall computing power and system energy efficiency, is becoming a frontier direction of interest in both the international academic and industrial communities.
To comprehensively showcase the latest academic achievements and technological advancements in the field of emerging computing chip design, the 2025 Issue 8 of Integrated Circuits and Embedded Systems has specially planned the “Special Issue on Emerging Computing Chip Design Research“. The content covers key technologies in high-efficiency emerging memory in-memory computing, hyperdimensional computing hardware design technologies, dedicated SoC architectures for large models and multi-agent tasks, chip optimization solutions in low-temperature environments, on-chip network communication interfaces and cache coherence mechanisms, efficient convolution acceleration technologies, and other cutting-edge directions. These studies not only focus on innovations in new devices and architectures but also consider system-level optimization needs such as high energy efficiency, low power consumption, and flexible adaptability, fully demonstrating the multidimensional exploration and continuous breakthroughs of Chinese research teams in the field of emerging computing chips, highlighting their strong technological innovation capabilities and application prospects.
The following 9 articles are included (you can access the full text by copying the links):
[1]Hyperdimensional Computing Hardware Design: Progress, Trends, and Prospects
https://service.jices.cn/CN/10.20193/j.ices2097-4191.2025.0047
[2]A Review of ROM-SRAM Hybrid In-Memory Computing Architecture
https://service.jices.cn/CN/10.20193/j.ices2097-4191.2025.0041
[3]A Review of Low-Temperature In-Memory Computing Chip Design
https://service.jices.cn/CN/10.20193/j.ices2097-4191.2025.0046
[4]End-to-End Domain-Specific SoC Design Based on Large Language Model Multi-Agent
https://service.jices.cn/CN/10.20193/j.ices2097-4191.2025.0043
[5]Efficient Winograd Convolution Hardware Design and Its Quantization Scheme
https://service.jices.cn/CN/10.20193/j.ices2097-4191.2025.0042
[6]Research on Time Domain In-Memory Computing Method for Spin Transfer Torque Magnetic Random Access Memory
https://service.jices.cn/CN/10.20193/j.ices2097-4191.2025.0045
[7]A Communication Interface Design for NoC and Flash Controller
https://service.jices.cn/CN/10.20193/j.ices2097-4191.2025.0052
[8]Design and Implementation of PCIe RP System Based on Cortex-M3 Kernel
https://service.jices.cn/CN/10.20193/j.ices2097-4191.2025.0051
[9]Accelerating the Snooping & Snooping Response Process of Cache Coherent Network on Chip with Multicast Adaptive Routing
https://service.jices.cn/CN/10.20193/j.ices2097-4191.2025.0044
01Hyperdimensional Computing Hardware Design: Progress, Trends, and Prospects
Tianyang Yu1,2, Bi Wu1,2, Ke Chen1,2, Wei Qiang Liu1,2
(1.Nanjing University of Aeronautics and Astronautics, School of Integrated Circuits; 2.Ministry of Industry and Information Technology Key Laboratory of Aerospace Integrated Circuits and Microsystems)
Abstract: Hyperdimensional computing is an emerging computing paradigm inspired by the human brain, characterized by low complexity, strong robustness, and strong interpretability, with broad application prospects in edge applications. Hyperdimensional computing simulates the information processing mechanism of the human brain, utilizing hyperdimensional vectors and simple logical operations to achieve complex cognitive functions, replacing the multi-layer complex structure of neural networks with a lightweight coding query process, providing a new technical path for high-energy-efficient edge artificial intelligence chips. This paper systematically elaborates on the theoretical foundation and algorithm evolution of hyperdimensional computing and discusses the feasibility of hardware acceleration for each step. Based on this, it provides a detailed introduction to dedicated hardware focusing on the query step, summarizing three implementation methods: FPGA, ASIC, and in-memory computing, and analyzing the advantages and disadvantages of different methods. Additionally, it introduces some recent research progress addressing common shortcomings of existing hyperdimensional query hardware. Finally, it presents the challenges faced by existing hyperdimensional computing hardware and prospects for future research directions.
Citation format: Yu T Y, Wu B, Chen K, et al. Hyperdimensional computing hardware: progress, trends and prospects[J]. Integrated Circuits and Embedded Systems, 2025, 25(8): 1-9. YU T Y, WU B, CHEN K, et al. Hyperdimensional computing hardware: progress, trends and prospects[J]. Integrated Circuits and Embedded Systems, 2025, 25(8): 1-9 (in Chinese).
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Content Source: JICES WeChat Official Account