(Source: Semiconductor Industry Observer)In May 2010, Andrew Waterman, a student at the University of California, Berkeley, sent an email to his professors. After experimenting with various teaching methods for a three-month project, he concluded:They should revive the nearly extinct microprocessor architecture DEC Alpha.“I don’t see how we can create anything new,” Waterman said. “This has nothing to do with ISA design—it’s an intellectually stimulating, creative, and technical task in itself. But developing compilers, operating systems, and porting a whole bunch of software? I think that’s a multi-billion dollar project, far beyond the understanding of a few scholars.”However, for Professor Krste Asanović, principles outweighed preferences: none of the existing ISAs met their needs. “In my view, there was no choice,” Asanović said. “Alpha was fast, but it had many architectural issues. I didn’t want those burdens.”Asanović speculated that the team had lingered too long between daunting commercial ISAs and less constrained but flawed or declining ISAs. Moore’s Law was slowing down, and Dennard scaling was about to end, necessitating specialization, customization, and parallelism. For this, they needed a fresh start.Asanović, Waterman, and graduate student Yunsup Lee discussed this in several emails. Ultimately, on May 18, 2010, Waterman compromised and accepted the risks of the new RISC.By the way, let me talk about the pun on RISC/risk. The title authors always benefit from it, but many are unaware that they are deliberately borrowing from Dave Patterson, the father of RISC. “We thought that government agencies known for funding high-risk, high-reward projects might be more favorable to us,” he told me.Patterson’s bet paid off when he created the first RISC architecture in 1980. In 2005, he founded the Par Lab at UC Berkeley, and five years later, RISC-V became the fifth major RISC ISA launched from the university under his guidance.In the 15 years since that Tuesday in 2010, RISC-V has not only become the third largest ISA on Earth but has also reached the Moon. High risk? Perhaps. High reward? Absolutely.Finding a Niche MarketThere are two common assumptions about RISC-V: that the team initially set out to build an open-source architecture and that they had to work hard to break free from academia’s constraints.“We stipulated that it had to be easy for small university teams to build, must be efficient, and easy to extend,” Asanović said. “The open requirement stemmed from our desire to share our results with friends through the Berkeley Software Distribution License. We wanted to push the academic computer architecture community back to real RTL hardware design, away from C models that might work or might not in the real world.”In the following years, RISC-V was purely a tool for parallel computing and processor design courses and research. But getting attention from academia outside Berkeley proved harder than expected. “Academia was very skeptical,” Asanović said. “To them, it was just another RISC ISA to learn. The fact that it was an open standard didn’t interest them—they wanted to teach what the industry was using. So they continued to focus on x86 development.”Everyone should know the “four giants of RISC-V”—Asanović, Waterman, Lee, Patterson. But one name you might not be familiar with is independent computer architect and Berkeley alumnus John Hauser. Asanović calls him the “fifth Beatle.”“Hauser played a significant role in shaping the ISA,” Asanović said. “The ecosystem owes him for the hypervisor in 2020 and the advanced interrupt architecture (AIA) in 2023. But we might also owe him an apology—because when he told us RISC-V would be a hit, we were not ready to believe him at all.”The first version of the RISC-V instruction manual was released in May 2011. However, it wasn’t until the team modified the ISA design in a few classes at UC Berkeley that they realized they had users outside of Par Lab. Suddenly, people on the other side of the Earth began questioning why they were changing certain things.“We knew this was a niche market,” Asanović said. “We just didn’t expect we would also fill that market for others. Many people focused on the technical aspects. Technically, is it better than other ISAs? In hindsight, RISC-V’s success did not stem from its technical advantages but from its openness. The real innovation was in the business model.”“We didn’t apply any pressure,” Waterman said. “If there was any influence, it was that we gently nudged it when the project was completed in 2014. Once it was done, we didn’t linger. After that, things really started to fall into place.”Industry Pull
Hot Chips 2014. From left to right, 5–Krste Asanović, 8–Yunsup Lee, 9–Andrew Waterman, 12–Dave PattersonThe IEEE Hot Chips 26 symposium held in Cupertino from August 10 to 12, 2014, was eye-opening. “We were very surprised by the appeal from the industry,” Asanović said. “When we attended the conference, we thought we would need to push hard for this. Clearly, we greatly underestimated the desire for an open ISA.” By the time the team held the first RISC-V workshop in Monterey in January 2015, the balance had truly shifted. “We expected very few participants from academia,” he said, “but in reality, 40 different companies attended the meeting.”But openness was not the only attraction. Another major complaint the team heard was the lack of flexibility in commercial ISAs. The main benefit of RISC-V to the industry was flexibility, not cost. However, RISC-V’s openness not only reduced costs but also eliminated cumbersome procedures. “Startups told us that signing contracts could take up to two years, which caught them off guard,” Asanović said. “With RISC-V, they could use it the same afternoon. We didn’t need to convince anyone that this was a good thing.”That year, Asanović and Patterson published a groundbreaking positioning paper titled “Instruction Sets Should Be Free: The Case For RISC-V,” further fueling the momentum. In the paper, they doubled down on openness, comparing it to open standards like TCP/IP, Ethernet, C language, and Linux.This paper had a profound impact on the industry. Mike Aaronson of Rumble Technologies read the paper and migrated an FPGA-based camera project from MIPS to RISC-V within three weeks. This became the first commercial product using RISC-V.At the fourth RISC-V workshop held in July 2016, NVIDIA announced plans to replace its proprietary Falcon core (used for power management and security tasks within graphics processing units (GPUs)) with RISC-V to meet 64-bit requirements. This move ultimately led to NVIDIA delivering one billion cores in 2024 alone. At the time, this may not have garnered much attention. But it was significant: a top semiconductor company chose RISC-V to perform critical internal functions.Months later, the fifth RISC-V workshop was held at a Google facility in Silicon Valley. “The number of participants from the industry far exceeded previous years, with 107 companies and 30 universities involved,” said Larry Lapides, executive director of RISC-V tool business at UK-based Imperas (now acquired by Synopsys). “The talks and exchanges I attended there convinced me that RISC-V was absolutely mature and worth adopting by the industry.”Today, Larry and CEO Simon Davidmann recognize future opportunities, positioning Imperas as a leading force in the RISC-V journey—dedicated to shaping its commercial future and supporting ecosystem development. Imperas’ commercial software tools, including simulators and verification suites, have been widely adopted across the ecosystem, accelerating its maturity and establishing best practices for design verification.Embracing EducationAs RISC-V’s momentum reached a critical point, academia finally acknowledged industry demand and accepted RISC-V as a teaching architecture.“We converted all course materials to RISC-V from top to bottom,” Asanović said. “And, as is often the case in academia, institutions would ‘borrow’ from the experiences of top universities. Making slides was easy, but building labs required a lot of energy, effort, and engineering work. Ultimately, when our full suite of resources began appearing in other university programs, we knew we had made an impact.”RISC-V gradually penetrated academia. Numerous institutions worldwide, including MIT, ETH Zurich, and the University of Bologna, adopted RISC-V in their teaching and research programs, developing course materials and lab exercises using its open-source features.As early as 2013, ETH Zurich and the University of Bologna launched a new open-source project called PULP (Parallel Ultra-Low Power) based on OpenRISC. The project was led by Luca Benini, head of the Digital Circuits and Systems Department at ETH Zurich, along with Frank K. Gürkaynak, a senior scientist at ETH Zurich and director of the Microelectronics Design Center, and project leader Professor Davide Rossi.Gürkaynak revealed, “The initial idea of PULP was not to design our own processor cores. But after several discussions with proprietary core vendors, we realized the need to open access to these cores for experimentation and to share our improvements with other partners.”The PULP team has been working hard to achieve the desired performance using OpenRISC. Subsequently, Rossi attended the first RISC-V workshop and training camp held in Monterey in 2015. “I realized that migrating from OpenRISC to RISC-V made a lot of sense because it had a much larger community,” he said. “By the end of 2015, we had migrated all cores to RISC-V.”“For those of us interested in researching new architectures and possibilities, the ability to freely develop, experiment, and share processor implementations has opened many doors for us,” Gürkaynak explained. “Based on our widely used and licensed implementations, we could collaborate more quickly in academia and industry. RISC-V benefits us, and we benefit RISC-V.”Leaving the LabAs RISC-V went global, it was time to separate it from Par Lab. “Everyone knows that graduate projects tend to die once the thesis is submitted,” Waterman said. “We needed something more stable to carry this standard.”Thus, the RISC-V Foundation was established in 2015 to promote openness, neutrality, and prevent fragmentation while establishing the ISA as a legal entity. Of course, it was also to ensure its sustainability as academia transitioned to new fields. One of the key figures in this transformation was Rick O’Connor, who played a central role in guiding the early governance model and served as the foundation’s founding executive director, helping lay the groundwork for industry-friendly architecture. Rick has been a strong advocate for moving RISC-V from the lab to an independent foundation, and his leadership has played a crucial role in bridging the gap between academic origins and commercial applications, ensuring the foundation could expand with the growing interest.