Source: Semiconductor Industry Observer
With the support of technical heavyweights, RISC-V is continuously growing, but it also brings challenges: encouraging CPU designers to maintain consistency and avoid the kind of fragmentation that occurred with MIPS and Android.
In light of this, RISC-V International, which coordinates the development of the open-source instruction set architecture (ISA), has sought guidance from its community and identified its priorities for the coming years.
Last week, the organization shared a survey on its mailing list to gather feedback to “help identify ISA gaps, formulate future expansion plans, and maintain compatibility between RISC-V applications.”
Mark Himelstein, Chief Technology Officer of RISC-V International, told The Register that the purpose of the survey is to understand what the community is doing and whether there is a strong desire to standardize some privately developed non-standard extensions.
RISC-V is sometimes referred to as the Linux of chips, with engineers around the world collaborating to design, set up, and improve the architecture.
RISC-V essentially consists of a set of specifications that define how compatible CPU cores should operate from a software perspective: the types of instructions available, their format in memory, and other core functionalities.
These specifications can be implemented royalty-free in processors and system-on-chips: semiconductor engineers decide how to build the pipelines and logic in their chips to run software built for RISC-V machines.
RISC-V adopts a modular approach: its ISA has a set of basic functionalities along with optional extensions, such as atomic operations and floating-point mathematics, which can be implemented in silicon as needed.
Some extensions are publicly released and approved by the community; engineers are also free to propose their own private custom extensions for their specific chips.
Depending on the design, adding functionalities at the CPU core extension level (e.g., instructions for accelerating AI operations) can avoid the need to develop and connect separate coprocessors and their interfaces.
Thus, chip developers can create and implement a mix of open and proprietary extensions for their RISC-V CPU cores. This is where fragmentation can occur.
A company may implement a set of standard RISC-V extensions in its processor family and add some custom, non-standard extensions that depend on specific applications.
These applications may struggle to run on RISC-V chips from another company that has not implemented those extensions, whether for reasons of approval or feasibility.
RISC-V International is keen to avoid this uncontrolled expansion of the ISA by encouraging teams to standardize their extensions in an open, collaborative manner, which seems to be a wise approach.
“Part of the reason for the survey is to figure out what else is out there. If it makes sense, we can get people to come together again and reduce these unqualified and non-standard extensions,” Himelstein said.
Standardization will encourage application developers to leverage RISC-V capabilities, knowing their code will run smoothly on a multitude of compatible chips. For commercial reasons, some organizations may still prefer to develop their proprietary extensions privately, either because they have thought of additions that others have not considered or because their chips will only run their code anyway.
Himelstein articulated this well.
“This is a contributor culture. If enough people are willing to [collaborate on standardizing extensions], then it will happen. If not, then it won’t, and people may go off and do their own thing, which is fine for us,” Himelstein said.
For example, if the survey shows sufficient enthusiasm for supporting 8-bit floating point or FP8 (which NVIDIA boasted about as a feature of its Hopper GPU last week), RISC-V International will begin discussions on standardizing such extensions. If not, people are free to propose their own custom extensions for it.
“There are other floating-point formats. Last year we did… half-precision IEEE floating point. But another one that is very popular in the embedded space, especially for machine learning, is bfloat16. We couldn’t do it last year. We’re working on it this year,” Himelstein said.
Imagination licenses GPU blueprints to system-on-chip manufacturers and has its own compatible RISC-V CPU design. The company states that components with approved extensions are key to building a robust RISC-V ecosystem.
“There are many unapproved custom extensions in the market that will hinder the widespread adoption of RISC-V,” Shreyas Derashri, Vice President of Computing at Imagination, told The Register. “Imagination fundamentally wants to strengthen the RISC-V ecosystem.”
If Imagination produces custom extensions, the company will work with RISC-V International to get those extensions approved. “This also includes work around RISC-V graphics extensions,” Derashri said.
RISC-V released 16 specifications last year, with more to come this year: what was closed and custom yesterday can be opened and standardized by the community tomorrow. “Just like in Linux, technology that may be proprietary today can solidify in five, three, or two years,” Himelstein said. “Everyone understands this game because we’ve been using it in computing for a long time.”
The RISC-V website also clearly names the status of specifications under development: whether they are under discussion, in development, open for review, frozen, or approved.
“We won’t rush to do something and then waste opcode space, having to redo something later. We can create a new extension, but we prefer to try to get it right,” Himelstein said.
It took six years for the RISC-V world to standardize the vector specification. Now, RISC-V leaders are trying to minimize the overlap of common functionalities related to special interest groups focused on graphics and machine learning, such as matrix operations.
“The vector team is creating a special interest group that will merge with these people and then decide what this thing looks like, because there is not only overlap but also overlap in some other areas of computer science,” Himelstein said.
Original link: https://www.theregister.com/2022/04/01/riscv_fragmentation/Welcome to join Imagination GPU and AI Communication Group 2
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