This article is based on a query from a certain STM32 user, slightly modified and organized. The content may be a bit extensive, involving STM32 timer synchronization applications, the correlation between timer trigger events and ADC, interrupt handling based on ADC events, and DMA transmission based on timer events. Ultimately, it requires attention to many details and flexible handling based on those details. The peripherals and functions involved are roughly illustrated in the block diagram below:
Currently, users are developing products with the STM32G474 chip. They use the TIM1 advanced timer, and the 4 channels CH1/CH2/CH3/CH4 are used for PWM output driving related applications. The following figure shows the output part of the functional block diagram of the STM32G4 series advanced timer.
Among them, the outputs of CH1/CH2/CH3/CH4 can drive external devices through GPIO, while CH5/CH6 only generate corresponding events and driving signals internally but cannot output practically. The output characteristics of CH5/CH6 are similar to those of CH1/CH2/CH3/CH4, except that they cannot produce actual output. The following example will utilize the CH5 OC signal and characteristics.
The user sets TIM1 to work in center-aligned counting mode. RCR=3, meaning that every 4 overflows [up or down] generate 1 timer update event [the lightning symbol in the following figure indicates the occurrence point of the update event].
Now there is a requirement to trigger ADC at a suitable time point during the upward counting segment of the counter. This time point will be dynamically adjusted based on the conversion results, and the adjusted sampling point is expected to take effect in the upward slope of the next counting cycle.
What event should be used to determine the sampling point of ADC? Since CH1/CH2/CH3/CH4 are used for other PWM output control, it is not convenient to extract them for separate modifications. At this point, we think of TIM1‘s CH5/CH6‘s OC5/OC6 signals and events; they do not perform specific PWM output driving, and using one of them to trigger ADC is a good choice. Below, we will take the CH5 OC5 signal and event as an example to introduce.
Now we need to set CCR5 to different values to determine the sampling point of ADC, while also adjusting CCR5 based on the results of ADC to further adjust the sampling point of ADC. Now we face a problem regarding the effective timing of CCR5.
We know that CCR registers can be enabled for preloading functionality. If we enable the preloading function of CCR5, due to RCR=3, we cannot guarantee that every modification of CCR5 will take effect in the upward slope of the next counting cycle.
If we disable the preloading function of CCR5, it will take effect immediately, but there are risks. It may trigger ADC multiple times during the same upward slope, which is obviously not suitable, as this will cause confusion in the processing and judgment of ADC results.
For example, as shown in the above figure, if the first trigger of ADC is at point A, after completing the ADC, we adjust the value of CCR5; if the adjusted value is smaller than the previous one, it would be better. If the adjusted value is larger than the previous one, it is very likely to trigger ADC again above the same slope.
It seems that whether to enable preloading for the CCR5 register is not very effective. What should we do?
At this point, we can consider introducing another auxiliary TIMER, allowing it to operate at the same frequency as TIM1 and start synchronously. Here, we let it work in up-counting mode and use a certain channel for PWM output [whether there is actual output is irrelevant], ensuring that its comparison event occurs at the same position as the center alignment point of TIM1. See the illustration below.
Specifically here, we choose TIM3 as the auxiliary timer, setting it to have the same counting period as TIM1. We choose its CH1 for PWM output with a fixed duty cycle of 50%, ensuring that the comparison event point of TIM3 remains synchronized with the center symmetry point of each cycle of TIM1. The following figure illustrates this [the blue PWM waveform is the output of TIM1-CH1 based on center-aligned counting, PWM2 mode, and high-active polarity, while the yellow PWM waveform is the output of TIM3 based on up-counting mode, PWM1 mode, and high-active polarity. The red triangular wave shows the real-time display of the TIM1 counter value.]:
We will disable the preloading function of the CCR5 register, and when we need to adjust CCR5 in the ADC interrupt, we first write to a specified memory buffer, then start the DMA transfer based on the comparison event of TIM3, allowing DMA to write the data stored in the memory buffer to the CCR5 register, ensuring that it can take effect in the next counting cycle. This way, we can avoid triggering ADC multiple times during the same upward slope and also avoid the issue where modifications to CCR5 may not take effect in a timely manner due to RCR=3.
At this point, the basic directional and functional issues have been resolved. Next, we should look at the specific implementation. To be honest, there is still a way to go.
TIM1 and TIM3 need to be started synchronously, establishing a master-slave relationship. This requires consulting the reference manual of the STM32G4 series to check the inline relationship between the TIMER signals. See the figure below:
I let TIM3 work in Trigger mode slave mode, with the counter enable signal of TIM1 as its trigger output, and this output is connected to TIM3‘s ITR0 as the start signal for TIM3‘s counter.
The following is the key configuration for TIM1 using CubeMx: [Note: the frequency parameters related to the TIMER below are quite large, mainly for debugging and observing results. Please set the frequency coefficients based on actual needs when applying.]
The following is the configuration for TIM3 using CubeMx:
From the configuration of the timing parameters of TIM1/TIM3, it is not difficult to see that both have the same counting period, which is 2000 counting clock units [Note: In center-aligned counting mode, one cycle is divided into two parts: up-counting and down-counting].
As mentioned earlier, the modification of the CCR5 register will be completed based on the comparison event of TIM3 through DMA. Therefore, we also need to configure DMA based on the comparison event of TIM3-CH1.
Here, we choose ADC1‘s ch1 as the verification test channel. Using the TIM1’s OC5 event or signal as the external trigger source for ADC. How do we associate the OC5 event or signal with the trigger for ADC?
Because ADC1 can choose TIM1‘s TRGO 2 as the trigger start signal, we can choose the OC5REF signal as the 2nd trigger output of TIM1 to trigger ADC. Meanwhile, ADC can also select the trigger polarity based on the signal originating from OC5Ref, which involves the TIM1-CH5 PWM configuration. The configuration for TIM1-CH5 PWM output is as follows [Note that the preloading function of CCR5 is disabled]:
Based on the above configuration, the OC5REF signal should look like this:
Since we require triggering ADC during the upward slope of the TIM1 counting, we choose the falling edge of the OC5Ref signal as the external trigger edge for ADC. Finally, the trigger configuration for ADC is as follows:
Additionally, I enabled the ADC EOC interrupt function, reading the results in the ADC interrupt and modifying the buffer value of CCR5, then starting the DMA transfer based on the comparison event of TIM3 to modify the value of CCR5 register, achieving dynamic adjustment of the ADC sampling point.
I made three different data modifications sequentially for CCR5 in the ADC interrupt to observe the effects. These 3 values are 400,600,800. The screenshot below is part of the reference code for the ADC conversion complete interrupt handling function.
The screenshot below shows the project created based on the above configuration, adding user code, and the output results after debugging:
The blue waveform is the TIM1-CHI1 PWM output, the yellow waveform is the TIM3-CHI1 PWM output, with a fixed duty cycle of 50%. The green waveform is the spike pulse sequence output through GPIO in each ADC interrupt. We can see that the distance of the green spikes from the center alignment line of TIM1 shows regular periodic changes, which corresponds to my periodic modifications to the value of TIM1-CCR5, and the trigger and conversion of ADC all occur during the upward slope of TIM1 counting.
With this introduction, the functionality that the STM32 user wants to achieve has been completed, and the functionality that needs to be implemented can basically be achieved. Of course, the implementation method above is not fixed; there can be other flexible adjustment schemes.
Finally, I would like to make an important reminder regarding the synchronous start of the previous two master-slave timers. Earlier, when I set the TIM1 and TIM3 ARR time parameters, the counting periods of both were the same to ensure that the comparison event point of TIM3 is always at the same position as the center alignment line of TIM1, maintaining the appearance shown in the figure below.
Otherwise, the distance between these two points will keep drifting, which will mess up the timing of our ADC operations. A common reason for this problem is that the timing periods set for TIM1 and TIM3 are not exactly the same. Specifically, for the center-aligned mode of TIM1, if ARR=1000, its counting length for one cycle is 2000 counting clocks. TIM3 needs to set the same counting period as it, and since it operates in up-counting mode, its ARR should be set to 2000-1. If it is set to 2000, it will cause a drift problem. The following two figures show the output conditions of TIM1->ARR=1000, TIM3->ARR=2000, with all other parameters exactly the same at two different times.
From the above waveforms, it is not difficult to see that the distance between the center symmetry line of TIM1 and the comparison event point of TIM3 is constantly changing, which is clearly a very bad situation for the current application, and the reasons are self-evident. Therefore, when setting the parameters for these two same-frequency timers, we must not get the ARR value wrong; being off by one will not work. Over time, you will feel the two specific events drifting noticeably in time.
Some people may find it hard to grasp this point. To give an analogy, if two workers are laying tiles, primarily using yellow tiles. At a certain moment, they start laying tiles simultaneously, advancing in parallel, and at the same speed. However, worker A, as illustrated below, places a green tile every 4 yellow tiles, while worker B places a red tile every 5 yellow tiles. Over time, we will see that the distance between the adjacent red and green tiles keeps changing, i.e., the distance between them is not fixed. If both workers lay tiles in the same fixed way, the distance between the red and green tiles will naturally remain unchanged.
With this discussion, I would like to add a few more points.
Earlier, I set both TIMERS to the same counting period and started synchronously. In fact, it is also possible to set TIM3’s period to exactly half of TIM1’s and start them synchronously. In this case, we can modify CCR5 based on the update event of TIM3.
Additionally, while I set the comparison event point of TIM3 at the same position as the center counting point of TIM1, this is not mandatory or fixed. Depending on the actual situation, it is also possible to shift the comparison event point of the auxiliary timer TIM3 slightly back, but maintaining a fixed relative position of the comparison event point within each cycle concerning the center symmetry line is essential.
Overall, the implementation of the above case requires minimal additional user code, but it demands a high level of understanding of the operational characteristics and details of the relevant peripherals. For example, introducing a suitable auxiliary timer, reasonably selecting the TRGO signal, appropriately configuring the PWM signal to match the ADC trigger point and polarity selection, and skillfully utilizing the DMA function, etc.
OK, that’s all for today’s sharing. I hope it helps. Let’s talk next time.
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Previous topics reading links:
1、STM32U5 TIMER+DMA+DAC application demonstration
2、Five questions and answers about STM32 applications
3、STM32H7 EXTI + SPI +DMA double buffering demonstration
4、Why does the program not run after changing the IDE?
5、Why is modifying the BASEPRI register ineffective?
