Author: Lei Silei, EETOP CPU Forum Moderator, Username: leishangwen,This article is from the author’s blog, the link can be clicked to read the original article.

RISC-V is an open-source instruction set architecture designed and released by the University of California, Berkeley (hereinafter referred to as UCB). Its goal is to become the Linux of the instruction set architecture field, with applications covering numerous fields such as IoT (Internet of Things) devices, desktop computers, and high-performance computers. It was created because UCB researchers found the following problems with current instruction set architectures during their research[1]. (1) Most instruction set architectures are patented, such as: x86, MIPS, Alpha, using these architectures requires authorization, which limits competition while stifling innovation. (2) Current instruction set architectures are quite complex and not suitable for academic research, and much of the complexity arises from poor design or historical baggage. (3) Current instruction set architectures are targeted at specific fields, such as: x86 is mainly for servers, ARM is mainly for mobile terminals, corresponding instruction set architectures have made a lot of domain-specific optimizations, lacking a unified architecture that can be applied across multiple fields. (4) Commercial instruction set architectures are easily affected by the development status of companies, for example: the Alpha architecture nearly disappeared with the acquisition of DEC. (5) Existing instruction set architectures are not convenient for custom extensions for specific applications. Therefore, UCB researchers Krste Asanovic, Andrew Waterman, and Yunsup Lee decided to design a new instruction-level architecture and chose to open-source it under BSD licensing, hoping to generate more innovative processors, more open-source processors, and thereby reduce the cost of electronic products[2].

Since its official release in 2014, RISC-V has attracted attention and participation from many companies, including Google, IBM, Oracle, and many well-known universities and research institutions, including the University of Cambridge, ETH Zurich, Indian Institute of Technology, and the Chinese Academy of Sciences. The ecosystem around RISC-V has gradually improved, and many open-source processors and SoCs based on the RISC-V architecture have emerged. These processors include both scalar and superscalar processors, as well as single-core and multi-core processors. This article will briefly introduce the basic design of the RISC-V architecture, followed by a detailed description of the current open-source processors and SoCs that adopt the RISC-V architecture.

1 RISC-V Introduction

1.1 RISC-V Basic Design

RISC-V is a typical three-operand, load-store RISC architecture, including three basic instruction sets and six extended instruction sets, as shown in Table 1, among which RV32E is a subset of RV32I and is not counted separately.

The suffix I in the name of the basic instruction set indicates Integer, meaning that any processor adopting the RISC-V architecture must implement a basic instruction set, and multiple extended instruction sets can be implemented as needed. For example, if RV32IM is implemented, it means that the 32-bit basic instruction set and multiplication and division extension instruction sets are implemented. If RV32IMAFD is implemented, then RV32G can be used to indicate that the general scalar processor instruction set is implemented. This article only introduces the basic situation of RV32I.

RV32I has 47 instructions that can meet the basic requirements for running modern operating systems. These 47 instructions can be categorized into the following types based on functionality.

(1) Integer operation instructions: Implement arithmetic, logic, comparison, and other operations.

(2) Branch transfer instructions: Implement conditional transfer, unconditional transfer, etc., without delay slots.

(3) Load/store instructions: Implement byte, half-word, and word load/store operations, all using register-relative addressing.

(4) Control and status register access instructions: Implement atomic read-write, atomic read-modify, atomic read-clear, etc., for system control and status registers.

(5) System call instructions: Implement system calls, debugging, and other functions.

1.2 RISC-V Advantages

1.2.1 Comparison with Open Source Instruction Set Architectures

Before the release of RISC-V, there were already several open-source instruction-level architectures, including SPARC V8 and OpenRISC, among which SUN’s open-source multicore multithreaded processor OpenSparcT1, OpenSparcT2, and the European Space Agency’s LEON3 adopted SPARC V8, and OpenRISC also has a similarly named open-source processor. RISC-V has been compared with the latter two, as shown in Table 2. In addition, OpenRISC’s license is GPL, which means that all instruction set modifications must be open-source. In contrast, RISC-V’s license is more permissive under the BSD License.

1.2.2 Comparison with Commercial Instruction Set Architectures UCB researchers designed an open-source processor Rocket based on the RISC-V instruction set architecture, which has been successfully fabricated 11 times. The performance comparison with the ARM Cortex-A5, which is also a scalar processor using the same TSMC 40nm process, is shown in Table 3. It can be seen that Rocket occupies a smaller area, uses less power, but has better performance.

2 Research Status of Open Source Processors Based on RISC-V

Currently, there are many open-source processors based on the RISC-V architecture, including both scalar processor Rocket and superscalar processor BOOM, as well as embedded-oriented Z-scale, PicoRV32, etc.

2.1 Scalar Processor——Rocket

Rocket is a 64-bit, 5-stage pipeline, in-order execution processor designed by UCB, with the following main features:

• Supports MMU, supports paged virtual memory, so it can port the Linux operating system.

• Has a compatible FPU with IEEE 754-2008 standards.

• Has branch prediction capabilities, with BTB (Branch Prediction Buff), BHT (Branch History Table), and RAS (Return Address Stack).

Rocket is written in Chisel (Constructing Hardware in a Scala Embedded Language), which is an open-source hardware programming language designed by UCB. It is a domain-specific application of the Scala language that can fully utilize Scala’s advantages, incorporating concepts such as object orientation, functional programming, parameterized types, and type inference into hardware programming languages, thus providing more powerful hardware development capabilities. In addition to being open-source, another advantage of Chisel is that hardware circuits written in Chisel can be compiled to obtain the corresponding Verilog design and also get the corresponding C++ simulator. By using Chisel to write Rocket, the corresponding software simulator can be easily obtained. Since Chisel is object-oriented, many classes of Rocket can be used directly by other open-source processors and open-source SoCs.

Rocket has been fabricated 11 times, and its performance reference is in Table 3.

2.2 Superscalar Out-of-Order Execution Processor——BOOM

BOOM (Berkeley Out-of-Order Machine) is a 64-bit superscalar, out-of-order execution processor designed by UCB, supporting RV64G, and is also written in Chisel. Utilizing the advantages of Chisel, it only used 9000 lines of code, and the pipeline can be divided into six stages: instruction fetch, decode/rename/instruction allocation, issue/read register, execute, memory access, and write-back.

With the help of Chisel, BOOM is a parameterizable superscalar processor, and configurable parameters include:

• Width of instruction fetch, decode, commit, and instruction issue.

• Size of reorder buffer (ROB) and physical registers.

• Depth of instruction fetch cache, RAS, BTB, load/store queues.

• Ordered or unordered issue.

• Number of ways in L1 cache.

• Size of MSHRs (Miss Status Handling Registers).

• Whether to enable L2 Cache.

UCB has already fabricated BOOM on a 40nm process, and the test results are shown in Table 4. It can be seen that BOOM’s performance is slightly better than that of the commercial product ARM Cortex-A9, reflected in smaller area and lower power consumption.

2.3 Processor Family——SHAKTI

SHAKTI^[4] is a project of the Indian Institute of Technology, aimed at designing a series of open-source processors based on RISC-V suitable for different application environments, as well as some IP cores for building SoCs. These processors include E-Class, C-Class, I-Class, M-Class, S-Class, H-Class, T-Class, and N-Class, with the first three already open-sourced, written in Bluespec System Verilog.

• E-Class: 32 bit scalar processor, 3 stage pipeline, supports RISC-V C (Compress) extension, aimed at ultra-low power processors.

• C-Class: 32 or 64 bit scalar processor, 3-8 stage pipeline, supports MMU, has fault tolerance, supports RISC-V C extension, also aimed at ultra-low power processors.

• I-Class: 64 bit, 1-8 core, out-of-order execution processor, shares L2 Cache, supports dual-threading, SIMD/VPU, aimed at general-purpose processors.

• M-Class: Enhanced version of I-Class, increases instruction issue size, supports four threads, up to 16 cores, aimed at general-purpose processors, low-end servers, and mobile applications.

• S-Class: 64 bit, superscalar multithreaded processor, supports L3 Cache, RapidIO, HMC (Hybrid Memory Cube), vector processing units, and coprocessors for database access, encryption algorithms, and machine learning, supports up to 64 cores, aimed at general-purpose processors and servers.

• H-Class: 64 bit, 32-128 cores, supports multithreading, in-order or out-of-order execution processors, with vector processing units, aimed at high-performance computing.

• T-Class: 64 or 128 bit processors, enhancing security by introducing Tags for memory.

• N-Class: Aimed at network data processing through custom extensions.

2.4 Embedded Application Processor——ORCA

PicoRV32 is a 32-bit scalar processor designed by VectorBlox, aimed at embedded applications, written in VHDL, implementing RV32IM, and can also remove the M extension, thus reducing chip resource usage, or even removing timer-related instructions to only implement RV32E. When ORCA is downloaded as a soft core to an FPGA, its resource usage and frequency are shown in Table 5.

2.5 Other Open Source Processors

(1) RI5CY

RI5CY is a compact 4-stage pipeline open-source processor jointly designed by ETH Zurich and the University of Bologna, implementing RV32IC, and the multiplication instruction mul in RV32M. Its goal is to serve as the processor core for the parallel ultra-low power processor project PULP (Parallel Ultra Low Power). Therefore, RI5CY adds many extensions over RISC-V, including hardware loops, multiply-accumulate, advanced arithmetic instructions, etc. It is fabricated using UMC’s 65nm process, with RI5CY’s frequency reaching 654MHz, and dynamic power consumption is 17.5uW/MHz^[6].

(2) RIDECORE

RIDECORE (RIsc-v Dynamic Execution CORE) is an out-of-order superscalar processor designed and released by Tokyo Institute of Technology, implementing RV32IM, with a 6-stage pipeline, including instruction fetch, decode, instruction allocation, issue, execution, and commit, capable of fetching two instructions simultaneously, decoding two instructions, and committing two instructions. It uses the Gshare branch prediction mechanism.

(3) Hwacha

Hwacha is a vector processor developed by UCB, which treats Hwacha as a non-standard extension of RISC-V, Xhwacha, and has been fabricated multiple times using 28nm and 45nm processes, with frequencies above 1.5GHz, and is still under development, modifying the OpenCL compiler to suit Hwacha, with plans to release its code in open-source form.

(4) f32c

f32c is a 32-bit, 5-stage pipeline scalar processor designed and released by the University of Zagreb, originally implementing the MIPS instruction set, later adding the RISC-V instruction set. The processor includes branch prediction and direct-mapped cache, and also releases an SDRAM controller, SRAM controller, video FrameBuffer, SPI controller, UART, GPIO, and other IP, written in VHDL. Using the f32c processor core, the University of Zagreb released the FPGArduino project, which turns an FPGA development board into an Arduino board, and can compile programs using the Arduino IDE.

(5) Z-scale/V-scale

Z-scale is a 32-bit, 3-stage pipeline, single-issue scalar processor released by UCB for embedded environments, implementing RV32IM, with both instruction and data buses being AHB-Lite. Z-scale is written in Chisel, utilizing code from Rocket, and only adding 604 lines of code to realize Z-scale. V-scale is the corresponding Verilog version of Z-scale.

(6) sodor

sodor is a series of 32-bit open-source processors released by UCB for teaching purposes, implemented in Chisel, which can easily obtain the corresponding C++ simulator. The sodor series includes five types of processors, namely single-cycle processor, 2-stage pipeline processor, 3-stage pipeline processor, 5-stage pipeline processor, and a processor capable of executing microcode.

(7) PicoRV32

PicoRV32 is an optimized size open-source processor designed and released by RISC-V developer Clifford Wolf, implementing RV32IMC, and can be configured to implement RV32E, RV32I, RV32IC, RV32IM, and RV32IMC depending on the environment. It has a selectable interrupt controller, characterized by its compact size, occupying 750-2000 LUTs on Xilinx7 series chips, with speeds reaching 250-400MHz.

(8) Tom Thumb

Tom Thumb is a 32-bit, 6-stage pipeline open-source processor designed and released by RISC-V developer maikmerten, implementing RV32I, aiming to minimize FPGA resource usage, occupying approximately 1200 LEs on Cyclone IV series FPGAs. It is written in VHDL.

(9) FlexPRET

FlexPRET^[7] is a 5-stage pipeline, multithreaded processor designed and released by UCB, aimed at real-time embedded applications, with the number of threads configurable from 1-8. To improve resource utilization of embedded processors, each hardware thread is marked as hard real-time or soft real-time, with hard real-time threads scheduled at fixed frequencies, and if no hard real-time threads are available, soft real-time threads are scheduled.

(10) YARVI

YARVI (Yet Another RISC-V Implementation) is a simple, 32-bit open-source processor designed and released by RISC-V developer Tommy Thorn, implementing RV32I, using Verilog as the development language. Its goal is not performance, but to implement RV32I clearly and accurately.

3 Research Status of Open Source SoCs Based on RISC-V

3.1 Rocket-Chip

UCB established the Rocket-Chip Generator project on GitHub to facilitate user learning and to conveniently reuse designed hardware modules, which includes Chisel, GCC, Rocket processor, and a series of bus units, peripherals, caches, etc., surrounding the Rocket, and adopts a parameterized configuration method, thus allowing easy creation of SoCs based on the Rocket processor with different performance requirements. It is written in Chisel, with the main submodules as follows.

• Chisel: UCB’s open-source hardware programming language.

• Hardfloat: Parameter-configurable, compliant with IEEE 754-2008 standards floating-point unit.

• Riscv-tools: Development tools including GCC, Newlib, and ported Linux.

• Rocket: Rocket processor, including L1 Cache.

• Uncore: Implements functional units that need to be tightly connected to Rocket, such as L2 Cache, L1 Coherence Hub, etc.

• Juntions: Implements conversion between interfaces of different protocols.

• Rocketchip: Top-level module, also implements conversion from internal bus TileLink to external bus AXI or AHB.

The previously mentioned BOOM and Z-scale can be obtained by configuring different parameters of Rocket-Chip.

3.2 LowRISC

LowRISC is a non-profit organization established by researchers from the University of Cambridge, primarily aimed at designing and releasing a 64-bit open-source SoC based on the RISC-V instruction set. Its members include collaborators of Raspberry Pi, so its goal is to make the designed SoC similar to Raspberry Pi, being inexpensive, feature-rich, and having a large user base. The SoC released by LowRISC is also named LowRISC, developed based on Rocket-Chip, with modified parts of the code written in System Verilog. The main features are as follows:

(1) Tagged Memory: Adds a Tag to each storage location, currently a double word (64bit) corresponding to one Tag (4bit), aimed at preventing control flow hijacking attacks, as well as other uses, such as garbage collection, setting watchpoints, etc. To implement Tagged Memory, LowRISC has added two instructions to read and write Tags for RISC-V. The 0.1 version released in April 2015 has this feature.

(2) Untethered: Early Rocket-Chip required the assistance of a general-purpose processor to start, to access peripherals such as serial ports, network ports, and SD cards. Untethered LowRISC solves the above issues by implementing memory mapping I/O, on-chip NASTI interconnect, etc. The 0.2 version released in November 2015 has this feature.

(3) Trace Debugging: Introduces Open SoC Debug, supporting Trace Debugging, capable of collecting instruction execution records for offline or online analysis. The 0.3 version released in July 2016 has this feature.

3.3 PULPino

PULPino is an open-source processor based on RISC-V released jointly by ETH Zurich and the University of Bologna, with its processor core RI5CY mentioned earlier. The original project designed by ETH Zurich and the University of Bologna was PULP, a multi-core SoC project, which was too complex, with many IPs and custom toolsets, making it inconvenient to open-source. Thus, the developers decided to first open-source a single-core SoC project, namely PULPino.

PULPino has an AXI interconnect bus, and also has an APB bus for connecting low-speed peripherals such as GPIO, UART, I2C controllers, SPI Master controllers, etc. The debug module supports Advanced Debug Unit. PULPino includes a Boot ROM, where BootLoader can be written, enabling it to read and execute programs from external Flash during startup.

3.4 RISC-V VHDL

RISC-V VHDL is an open-source SoC based on Rocket released by the Russian GNSS Sensor company, originally a project from Moscow Institute of Physics and Technology. The processor core of this project directly uses Rocket, which can be configured to have only L1Cache or to include L2Cache. On this basis, it provides a large number of IP cores, adopting a plug-and-play approach similar to the LEON3 GRLIB library. All IP cores are plug-and-play, and RISC-V VHDL provides an AXI bus, with all IP cores mounted on this bus.

Most of the IP cores in RISC-V VHDL are open-source, with the only commercial one being GNSSLIB, a library related to positioning and navigation, which is also a feature of RISC-V VHDL.

Conclusion

RISC-V is developing rapidly. In addition to the numerous open-source processors and SoCs based on RISC-V mentioned earlier, many commercial processors are also planning to adopt the RISC-V instruction set architecture, such as PulSAR^[8], which adopts a heterogeneous multiprocessor structure that includes two scalar processors Rocket and two superscalar out-of-order execution processors BOOM.

RISC-V’s development benefits from its design, which draws on nearly 40 years of experience and lessons from RISC, making the architectural design more reasonable. It also benefits from the increasingly mature software ecosystem. UCB provides open-source compilers for RISC-V, such as GCC and LLVM, as well as open-source simulators like Spike and QEMU, and the community has ported operating systems such as FreeBSD, Debian, Gentoo, Yocto, and Genode to RISC-V.

At the 4th RISC-V Special Symposium, the establishment of the RISC-V Foundation was announced, which includes many powerful commercial companies and well-known research institutions, including the Chinese Academy of Sciences. It is foreseeable that RISC-V is about to enter a stage of rapid development, and breakthroughs are expected in the following aspects.

(1) Several mature, commercializable chips based on RISC-V architecture will be launched and widely used.

(2) Performance approaching mainstream desktop processors.

(3) Heterogeneous systems composed of mainstream processors and open-source processors based on RISC-V architecture.

(4) More stable and reliable operating systems ported to RISC-V architecture.

(5) Multi-core parallel computing using hundreds of simple RISC-V cores.

(6) RISC-V will be used as an example in computer education.

(7) Debugging functions will be further strengthened.

For domestic purposes, RISC-V provides a good reference and is a great opportunity, with many lessons to learn to achieve self-controllable processors.

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