The chairman of RISC-V made it clear: RISC-V is not an open-source processor? It certainly is not a processor; it refers to an instruction set.
Recently, there have been articles online that misinterpret RISC-V and open-source processors, causing confusion among some readers. This article will clarify concepts such as the instruction set of processors, microarchitecture implementation, and open-source models, as well as their relationship with RISC-V, hoping to help readers better understand RISC-V and open-source processors. Here are a few key points:
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The instruction set specification (Specification) and processor implementation (Implementation) are two different levels of concepts and should be distinguished. The instruction set (ISA) is a standard specification, often recorded in a book or a few pages, while the processor implementation is the source code completed based on the instruction set specification. RISC-V is an instruction set specification.
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We can design and implement processor microarchitecture based on x86/ARM/RISC-V instruction sets to form source code, and eventually create chip products. The intellectual property of the instruction set specification and processor implementation is independent and cannot be confused. (See sections two and three for details)
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“RISC-V is open-source” means that the instruction set specification is open, free, and accessible (open and free), which is fundamentally different from x86 and ARM instruction sets, but does not imply that specific processor implementations are also open-source and free.
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Based on the RISC-V instruction set specification, both open-source communities can develop open-source free versions of processor implementations (such as the Rocket core developed by Berkeley) and commercial companies can develop paid licensed versions of processor implementations (such as the domestic Pingtouge Xuantie 910, Xilinx N200 core, and Yuxi Weihe WH-32 core, etc.) (See section three for details).
1. Analysis of a Recent Online Article
Recently, an article titled “The Chairman of RISC-V Made It Clear: RISC-V Is Not an Open-Source Processor” appeared online, which contains some misconceptions about RISC-V and open-source processors, causing confusion among some readers. Here are some interpretations of the viewpoints mentioned in that article:
Question 1: The article mentions that “Krste Asanovic, chairman of the RISC-V Foundation, clarified that ‘RISC-V is not open-source’,” is this true?
Krste Asanovic explained in the article that: a) RISC-V is an instruction set, not a processor; b) RISC-V can be used to create both open-source processors and commercial processors. And the point that “RISC-V is open-source” has not changed from the beginning. Generally, people understand “open-source” as publicly available and free to use code or information. From this perspective, RISC-V, as a set of instruction set specifications, although it has no source code, is indeed open and free (open and free), which is the same for both open-source RISC-V processors and commercial RISC-V processors. Therefore, the conclusion that “RISC-V is open-source” is beyond doubt.
Moreover, RISC-V is not only open-source itself, but its relationship with the entire open-source chip ecosystem is also very close. While not all projects based on RISC-V are open-source (some are commercial processors and software), at least they are deeply involved in and use open-source (processor chips or software), and it can even be said that RISC-V can represent the entire open-source chip ecosystem in specific scenarios.
Question 2: Do processors designed based on RISC-V need to be paid for in the future?
As an open, free instruction set, RISC-V supports multiple modes of microarchitecture design (see section three of this article for details). People can design open-source processors based on RISC-V, or they can create commercial processors (not open-sourced, sold or used). It is precisely the open and free characteristics of RISC-V that have led to a hundred flowers blooming in the chip industry. The RISC-V Foundation is only responsible for the RISC-V instruction set specification, neither designing microarchitectures nor producing chips. What kind of chips to design and produce is up to other companies, and has nothing to do with the foundation; whether to open-source or charge has nothing to do with the foundation either. Krste Asanovic just wants to tell everyone that RISC-V can be used to create both open-source and commercial processors, and not all RISC-V processors are open-source and free. [Note: Here, open-source and commercial refer only to whether they are open or charged, and both can achieve equivalent performance.]
Question 3: RISC-V originated in the U.S., is there a risk of regulation?
The RISC-V instruction set is an open-source, free interface specification and will not be affected by U.S. regulation. However, processors developed based on RISC-V exist in the form of commodities, so RISC-V processors developed by U.S. companies will be subject to U.S. export controls. On the other hand, RISC-V processors independently developed by companies outside the U.S. (including Europe, China, etc.) are not considered U.S. commodities and are therefore not subject to U.S. export control regulations. For example, the self-developed RISC-V processor Xuantie 910 by Pingtouge is not affected by U.S. export controls.
Additionally, historically, the TCP/IP protocol is quite similar to today’s RISC-V. The TCP/IP protocol was developed with funding from the U.S. Department of Defense’s Advanced Research Projects Agency (DARPA) and is a model of open standards. Around the world, the Internet, which connects billions of people today, was built based on this protocol, and China has built its network based on the TCP/IP protocol without being affected by U.S. export controls; Chinese companies developing switches and routers based on TCP/IP are also not subject to U.S. export controls.
Finally, in November 2019, the RISC-V Foundation announced that it would relocate its headquarters to Switzerland, which also conveys the message of adhering to openness and freedom and serving the world.
2. What is an Instruction Set and What Role Does It Play?
Instruction Set (ISA): The instruction set is the interface between software and hardware, a set of standard specifications (published in document form), and does not have a physical entity. We can design processor chips and corresponding software systems based on this specification and eventually form products. Common instruction sets include x86 (commonly used in desktops and servers), ARM (commonly used in mobile embedded devices, smartphones, tablets, etc.), and RISC-V (the rising open instruction set) [4].
Figure 1: The instruction set is the interface between software and hardware
The relationship between software and hardware is like that of nuts and bolts. If we view software as the nut and hardware as the bolt, then the instruction set (ISA) is the size specification for the connection between the nut and the bolt. If both the nut and the bolt are designed according to the same size (i.e., the same specification), even if produced by different manufacturers, it can ensure that all nuts can ultimately fit onto the bolts.
As shown in Figure 1, the instruction set carries the entire software ecosystem upwards and specifies the entire hardware ecosystem represented by processor chips downwards. Based on an instruction set specification, designing a processor allows for the same software code written according to that instruction set specification to run on it. Thus, when we mention an instruction set, we sometimes refer to the entire software and hardware ecosystem behind it, including peripheral chips, operating systems, compilers, and various application software (browsers, games, etc.). It has been proven that the success of any chip in market competition largely depends on its ecosystem.
3. What is the Relationship Between RISC-V and Open-Source Processors?
First of all, a processor chip contains three levels: instruction set (ISA), microarchitecture design, and product.
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Instruction Set (ISA), is a specification standard, often recorded in a book or a few pages;
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Microarchitecture Design, also commonly referred to as processor implementation, is the specific implementation corresponding to a design method and its source code;
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Product, is the instantiation of microarchitecture design, for example, Huawei designed the Kirin 990 chip based on the ARM instruction set and Cortex-A76 microarchitecture.
Figure 2: Analysis of the relationship between instruction set, microarchitecture design, and product
Strictly speaking, “open-source” is short for “open-source code,” while the instruction set is just a few pages of paper and does not have source code. The open-source processors we usually refer to are those with open-source microarchitecture design code.
As shown in Figure 2, further dividing the instruction set standard and architecture design into three categories: Open & Free, Licensable, Closed. Thus, we can see that Intel belongs to a closed instruction set + closed design, ARM belongs to a licensable instruction set + licensable design, but obtaining a license is quite expensive, often requiring hundreds of thousands or even millions of dollars [5].
RISC-V provides the world with the option of an open and free instruction set + open and free design. According to the first row of Figure 2, we can see that only with an open-source instruction set can there be an open-source microarchitecture design, i.e., the green box. It is important to emphasize that RISC-V itself is a standard specification, similar to C/C++ language standards, POSIX system calls, etc. It is open by nature, and anyone can implement their own processors based on these standards. However, one point that needs to be clarified is that even if they are all based on open-source instruction sets (such as RISC-V), there are still three different business models. Analyzing the first row of Figure 3, the open and free instruction set (RISC-V) includes three modes of microarchitecture design [5]:
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Open-source model, Berkeley’s Rocket Chip, Cambridge University’s lowRISC, and the hummingbird E203 RISC-V cores have also open-sourced their RTL-level source code, and these designs belong to the green box;
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Licensing model, SiFive, Andes Technology, and Alibaba’s RISC-V cores can be licensed to third parties for use, but the RTL-level source code is not open-sourced, falling into the yellow box;
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Closed model, companies like Google and NVIDIA extensively use RISC-V cores internally as MCUs, but they do not open their IP and source code externally, which falls into the red box.
In summary, the instruction set is open and free, but the microarchitecture design can choose to be open-sourced for everyone (open-source model); can choose to charge and license it to other companies for production (licensing model); or can choose not to license it and produce it themselves (closed model). RISC-V provides everyone with completely free and open choices. The open-source model’s green box is what we often refer to as open-source processor designs based on RISC-V.
4. Why Develop Open-Source Processors?
The importance of open-source processor projects is unquestionable; they will greatly reduce the development cycle and threshold for chips, allowing everyone to focus on incremental innovation without having to explore how to build a chip from scratch, speeding up the iteration cycle, and quickly launching products to market by leveraging RISC-V’s software ecosystem. Developing new open-source processor projects, setting an open-source mainline, and gaining more technological and ecological advantages are crucial for enhancing the voice and dominance of domestic RISC-V companies in the international RISC-V industry [6].
5. Citations and References
[1] The chairman of RISC-V made it clear: RISC-V is not an open-source processor;
https://www.toutiao.com/a6800643802252968456/
[2] RISC-V is not an “open-source processor”;
https://riscv.org/2020/02/risc-v-is-not-an-open-source-processor-krste-asanovic-chairman-of-the-board-risc-v/
[3] RISC-V Foundation relocates to Switzerland for technical neutrality;
https://www.infoq.cn/article/ko94LqU9lXblLXGVTamQ
[4] Some doubts and interpretations about RISC-V;
[5] Summary of the Future Vision Seminar: Open-Source Chips and Agile Development for Next-Generation Computing;
http://blog.sciencenet.cn/blog-414166-1192579.html
[6] Report on the Progress of Open Instruction Sets and Open-Source Chips;
http://crva.ict.ac.cn/documents/OpenISA-OpenSourceChip-Report.pdf
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Background Introduction: This article is written by Bao Yungang, a researcher at the Institute of Computing Technology, Chinese Academy of Sciences, director of the Advanced Computer Systems Research Center, and a professor at the University of Chinese Academy of Sciences. His main research areas include open-source processors and agile design, data center architecture, etc., and he has led the development of several systems that have reached international advanced levels. Related technologies have been applied in domestic and foreign enterprises such as Huawei, Alibaba, and Intel. He has received the “CCF-Intel Young Scholar” award, delivered a 45-minute keynote speech at the ARM 2018 Global Research Summit, and is an excellent member of the Youth Innovation Promotion Association of the Chinese Academy of Sciences, receiving the “CCF-IEEE CS” Young Scientist Award and the “National Good Youth” honor from the Central Committee of the Communist Youth League.The article was published on March 9, 2020, in the WeChat public account China Open Instruction Ecosystem RISC-V Alliance (Interpretations of RISC-V and Open-Source Processors), authorized for reprint by Fengyun Voice.
