RP1: the silicon controlling Raspberry Pi 5 I/O, designed here at Raspberry Pi

Raspberry Pi 5 is the most complicated, and expensive, engineering program we’ve ever undertaken at Raspberry Pi, spanning over seven years, and costing on the order of $25 million. It’s also our first flagship product to make use of silicon designed in-house here at Raspberry Pi, in the form of the RP1 I/O controller.

RP1 is an incredibly intricate design, combining all of the outward-facing analogue interfaces required to build a Raspberry Pi, and the respective digital controllers, into a single 20mm² die, implemented on TSMC’s 40LP process. It provides MIPI camera input and display output, USB 2.0 and 3.0, analogue video output, and a Gigabit Ethernet MAC; and it provides enough 3V3-failsafe general-purpose I/O pins, and the various low-speed digital peripherals, to drive our standard 40-pin GPIO header. These components are connected via an AMBA AXI fabric to a PCI Express device controller, and thence to the BCM2712 application processor. Each component has its own clocking requirements, and implementation constraints which must be obeyed for it to function correctly.

Some initial documentation

Today we’re releasing some initial documentation around the RP1 silicon. Like the peripherals documentation for the Broadcom BCM2711, which powers Raspberry Pi 4, this release is aimed at people implementing drivers for Raspberry Pi 5. That means that, unlike our documentation around our microcontroller product RP2040, today’s release doesn’t tell you everything about the RP1 silicon that you might want to know; instead, it’s there to help you port an operating system and make use of the features of Raspberry Pi 5. While we are looking at exposing more of the features of RP1, both in software and with further documentation, that’s going to be something you might see a little later on.

Raspberry Pi’s silicon engineering team

Over the last decade, we’ve built an exceptional silicon engineering team, which was able to tackle the challenge of building RP1. But the same capabilities also allowed us to build our RP2040 microcontroller: RP1 and RP2040 share a certain amount of internal infrastructure, and both were built using our in-house SPIV chip-assembly toolchain. And having RP2040 in the market for over two years has served to pipe clean many of the processes required to build silicon at scale, making for a much smoother RP1 production ramp.

In the video below, our Chief Technology Officer (Hardware) James Adams and I are joined by Liam Fraser, ASIC team member and SPIV creator, to talk about RP1, and the development process that produced it.