Recently, I introduced the open-source base station O-RAN.
Today, I’m going to introduce another open-source concept, which is the current celebrity in the semiconductor industry, often referred to as the “open-source chip” RISC-V.
Speaking of chips, since the ZTE ban by the U.S., the attention on chips has reached an unprecedented height among the Chinese people. It seems that overnight, everyone realized the importance of chips and experienced the serious consequences of a “chip shortage”.
This year, Huawei was again targeted by the U.S. government and placed on the entity list, sparking nationwide discussions about the capability for independent chip research and development.
Due to a combination of internal and external factors, the country has significantly increased investment in the chip field, and more and more companies are beginning to pay attention to chip R&D investment.
At this critical juncture, RISC-V is likely to play a very key role.
What exactly is RISC-V?
RISC-V is generally pronounced as: risk five. V stands for the Roman numeral 5.
Many people mention RISC-V and say it is an open-source chip. Actually, this statement is incorrect. To be precise, RISC-V is an open-source instruction set architecture based on the principle of “Reduced Instruction Set (RISC)”.
Don’t worry! I can explain it simply! —
An instruction set, for a CPU, is a collection of program instructions that serve as a bridge between software and underlying hardware. The instruction set is stored within the CPU, guiding it to perform calculations and helping it run more efficiently.
In a PC, the CPU chip (central processing unit)
In our commonly used desktop computers or servers, the main CPUs used are from Intel and AMD. These CPUs use instruction sets that belong to “CISC Complex Instruction Set”.CISC stands for Complex Instruction Set Computer.
A CPU can support many types of instruction sets.
Early computer CPUs were all based on CISC architecture.
At that time, the technology of compilers was not mature, and programs were written directly in machine code or assembly language. To reduce program design time, single instructions were gradually developed to handle complex operations. Designers only needed to write simple instructions and let the CPU execute them.
However, later it was discovered that only about 20% of the instructions in the entire instruction set were frequently used, accounting for about 80% of the entire program; the remaining 80% of the instructions only accounted for 20% of the program. (Typical Pareto Principle)
Thus, in 1979, Professor David Patterson from the University of California, Berkeley proposed the idea of RISC, advocating that hardware should focus on accelerating commonly used instructions while utilizing common instructions to combine more complex instructions.
RISC stands for Reduced Instruction Set Computer.
In simple terms, CISC has strong processing capabilities and is suitable for desktop computers and servers. But high performance also brings high power consumption issues.
On the other hand, RISC simplifies the types and formats of CISC instructions, simplifies addressing methods, achieving energy-saving and efficient results, suitable for portable electronic products or IoT products such as mobile phones, tablets, and digital cameras.
In the 1980s, ARM started making its own chips based on the RISC architecture, eventually rising step by step to defeat Intel and become the current king of mobile chips. Nowadays, most mobile terminals and IoT device chips, including Huawei Kirin and Qualcomm Snapdragon, are designed based on ARM architecture.
Note that I am referring to ARM’s architecture, not ARM’s chip products.
The business model of ARM is very special. It designs chip architectures, equivalent to drawing engineering blueprints, and sells these blueprints to major chip manufacturing companies, such as Huawei. These companies modify based on the original blueprints to design their desired chips and send them to chip factories (such as TSMC) for production.
Of course, ARM’s blueprints are not free. Not only are they not free, but they are also very expensive.
According to online information, ARM’s licensing fees range from hundreds of thousands to tens of millions of dollars. A chip startup company in France once stated in an interview that if they used ARM architecture, they would spend $15 million on licensing fees. (This statement was later denied by ARM, but in any case, it is not cheap.)
Nowadays, with the rapid development of technologies like 5G, IoT, and artificial intelligence, more and more companies are beginning to produce and manufacture terminals and modules for various vertical industries.
This means that more and more companies are forced to accept the “exploitation” of ARM or other chip giants.
Large enterprises can handle it, but for many small and medium-sized enterprises or even startups, this is almost a complete closure of the forward path.
At this time, some brave individuals stood up.
In 2010, a research team from the University of California, Berkeley was preparing to launch a new project. When choosing an instruction set for the new project, they found that the x86 instruction set was tightly controlled by Intel, the ARM instruction set was very expensive, and MIPS, SPARC, and PowerPC also had intellectual property issues.
In this situation, the research team resolutely decided to start from scratch and design a completely new instruction set.
To outsiders, this seemed like a daunting task. However, the Berkeley research team only gathered a 4-member group and completed the development of the RISC-V instruction set in just three months.
Although it seemed very easy, there were prerequisites. RISC-V is called V (Five) because it had previously gone through I, II, III, IV.
The person leading the development of these RISC instruction sets was none other than Professor David Patterson from Berkeley. If you scroll back in this article, you will find that he is the true founder of the RISC instruction set. The groundbreaking paper that formally proposed the design idea of the Reduced Instruction Set was co-authored by him and another scholar named Ditzel.
Professor David Patterson later received the Turing Award.
It is precisely because of the relevant technological accumulation that the Berkeley team could produce RISC-V in a short period.
The first generation RISC-I processor was already produced in 1981.
The RISC-V instruction set is very concise and flexible. Its first version contains less than 50 instructions, which can be used to implement a processor with basic functions such as fixed-point calculations and privileged modes. If users need it, they can also customize new instructions based on their needs.
After all, universities are universities, and their profit-seeking mindset is not that strong. Moreover, the research team itself really had no money or personnel to maintain it. Therefore, after developing the RISC-V instruction set, the research team decided to open it up completely, using the BSD License for open-source protocol.
The BSD (Berkeley Software Distribution) open-source protocol is a very permissive protocol, almost allowing “anything goes”. It allows users to modify and redistribute open-source code and allows the development of commercial software based on the open-source code for release and sale.
This means that anyone can design and develop chips based on the RISC-V instruction set and sell them without having to pay licensing fees.
This is exciting, and a large number of companies began to join the research and secondary development of RISC-V.
In just a few years, companies such as Google, Huawei, IBM, Micron, NVIDIA, Qualcomm, Samsung, Western Digital, and academic institutions like the University of California, Berkeley, MIT, Princeton University, ETH Zurich, Indian Institute of Technology, Lawrence Livermore National Laboratory, Nanyang Technological University in Singapore, and the Institute of Computing Technology of the Chinese Academy of Sciences have all joined the RISC-V Foundation.
Currently, the RISC-V Foundation has a total of 235 member units, including 18 platinum members (data as of July 10, 2019). These member units include semiconductor design and manufacturing companies, system integrators, equipment manufacturers, military enterprises, research institutions, and universities, indicating that the influence of RISC-V is continuously expanding.
As mentioned earlier, RISC-V has very important significance for our country’s chip industry.
For a long time, our country’s chip R&D has been constrained. If domestic companies or research institutions can utilize the open-source RISC-V to produce chips with basic independent intellectual property rights, or cultivate the corresponding ecological environment, it will greatly benefit the Chinese semiconductor industry in making a leapfrog development.
Therefore, more than 20 domestic enterprises and institutions, including the Institute of Computing Technology of the Chinese Academy of Sciences, Huawei, and Alibaba Group, have chosen to join the RISC-V Foundation. Alibaba is also one of the platinum members.
In July 2018, the Shanghai Economic and Information Commission issued the first domestic policy supporting RISC-V. In October, the China RISC-V Industry Alliance was established. In terms of products, Zhongtian Micro and Huami Technology successively released processors based on the RISC-V instruction set.
Based on RISC-V development is the Huangshan No. 1 (Huami), the world’s first artificial intelligence chip in the wearable field.
Our neighbor India has shown even greater enthusiasm for RISC-V. In recent years, government-funded processor-related projects in India have begun to lean towards RISC-V. RISC-V has become India’s national instruction set.
The rapid development of RISC-V has put a lot of pressure on companies like ARM.
Last June, ARM specifically created a domain named riscv-basics.com, where the content theme was “Five things to consider before designing a system chip,” attacking RISC-V from the aspects of cost, ecosystem, fragmentation risk, security, and design assurance.
On the RISC-V side, they countered by creating a domain named arm-basics.com, titled “Six things to consider before designing a system chip” (adding community support to the five points listed by ARM) to fight back against ARM.
A few days later, ARM’s riscv-basics.com website quietly went offline.
Although RISC-V won this brief “battle”, the five aspects raised by ARM are not without reason, especially the fragmentation issue. As an open-source technology, RISC-V indeed faces challenges in avoiding fragmentation.
(Fragmentation: Because RISC-V allows users to arbitrarily add new instructions, if this trend continues, many chip manufacturers developing RISC-V architecture processors may belong to the same RISC-V system, but they may not be compatible with the same version of software in actual applications.)
In summary, RISC-V can be seen as a vibrant young disruptor. It is unrealistic to expect it to compete with traditional giants in a short time. However, it has raised the banner to break the monopoly, injecting fresh vitality into the stagnant industry ecology, which deserves our applause and learning.
A spark can start a prairie fire, perhaps this disruptor may really become a leader in the future.
