Overview of Linux Device Drivers: Ethernet and PCI
EthernetThe Ethernet interface consists of MAC (Media Access Controller) and PHY (Physical Interface Transceiver). The Ethernet MAC is defined by the IEEE 802.3 Ethernet standard, implementing the data link layer. Common MACs support two rates of 10Mbit/s or 100Mbit/s. Gigabit Ethernet (also known as 1000Base-T) is the next generation technology of Fast Ethernet, increasing the network speed to 1000 Mbit/s. Gigabit Ethernet was released under IEEE 802.3z and 802.3ab as an extension of the IEEE 802.3 standard.The connection between MAC and PHY uses MII (Media Independent Interface), which is an industry standard defined by IEEE-802.3, including one data interface and one management interface between MAC and PHY. The data interface consists of two independent channels for sending and receiving, each with its own data, clock, and control signals, requiring a total of 16 signals for MII data interface. The MII management interface contains two signals: one is a clock signal, and the other is a data signal. Through the management interface, the upper layer can monitor and control the PHY.The hardware circuit principle of an Ethernet interface is shown in the diagram, sequentially from CPU to the final interface: CPU, MAC, PHY, Ethernet isolation transformer, RJ45 socket. The Ethernet isolation transformer is a magnetic component between the Ethernet transceiver chip and the connector, serving functions such as signal transmission, impedance matching, waveform correction, signal noise suppression, and high voltage isolation.Many processors integrate MAC or both MAC and PHY, and many Ethernet controller chips also integrate MAC and PHY.PCI and PCI-EPCI (Peripheral Component Interconnect) is a local bus introduced by Intel in 1991 as a general bus interface standard, widely used in current computer systems. The PCI bus has the following characteristics.● The data bus is 32 bits wide, expandable to 64 bits.● Supports burst mode transmission. Burst mode transmission means that after obtaining bus control, multiple data transmissions occur continuously. In burst mode, only the starting address of the destination needs to be provided, and after accessing the first data, the second to nth data will be automatically addressed and transmitted based on certain rules. In contrast, the single-cycle mode transmits only one data per bus cycle.● Bus operations are parallel with processor-memory subsystem operations.● Uses centralized bus arbitration.● Supports fully automatic configuration and resource allocation. PCI cards have a device information register set that provides the system with card information, enabling plug-and-play functionality.● The PCI bus specification is independent of microprocessors, making it highly versatile.● PCI devices can fully control the bus as master devices.The diagram shows a typical logical schematic of a computer system based on the PCI bus, with various parts connected via the PCI bus and PCI-PCI bridge. The CPU and RAM are connected to PCI bus 0 (the main PCI bus) through the PCI bridge, while graphics cards with PCI interfaces can connect directly to the main PCI bus. The PCI-PCI bridge is a special PCI device responsible for connecting PCI bus 0 and PCI bus 1 (the subordinate PCI bus), where PCI bus 1 is usually referred to as downstream and PCI bus 0 as upstream. To maintain compatibility with the older ISA bus standard, the PCI bus can also connect to the ISA bus via a PCI-ISA bridge, thus supporting older ISA devices.When a PCI card is powered on, the configuration space on the card can be accessed. The PCI configuration space stores all the information needed for the card to operate, such as manufacturer, card function, resource requirements, processing capabilities, number of functional modules, and master card capabilities. By reading and programming this space information, the configuration of the PCI card can be completed.As shown in the diagram, the PCI configuration space is a total of 256 bytes, mainly including the following information.● Manufacturer ID: Assigned to the manufacturer by the PCI organization.● Device ID: A number assigned to the card according to product classification.● Class Code: A classification code for the card’s function, such as graphics card, display card, decompression card, etc.● Request for memory space: PCI cards have memory or memory-mapped registers and I/O space, and to allow driver programs and applications to access them, a segment of CPU memory must be requested for addressing. The base address register in the configuration space is used for this purpose.● Request for I/O space: The base address register in the configuration space is used to request system I/O space.● Interrupt resource request: The interrupt pins and interrupt lines in the configuration space are used to request interrupt resources from the system. The interrupt pin register at offset 3Dh indicates which interrupt pin is used by the PCI device, with the correspondence being 1—INTA#, 2—INTB#, 3—INTC#, 4—INTD#.PCI-E (PCI Express) is a next-generation bus interface proposed by Intel. PCI Express uses the currently popular point-to-point serial connection in the industry, compared to PCI and earlier computer buses’ shared parallel architecture, each device has its own dedicated connection, using serial transmission of data, eliminating the need to request bandwidth from the entire bus, and can achieve a very high data transfer rate, reaching a bandwidth that PCI cannot provide.PCI Express is software-layer compatible with current PCI technology and devices, supporting the initialization of PCI devices and memory modules, meaning there is no need to overhaul existing drivers and operating systems to support PCI Express devices.For more information, you can follow the public account “Auto Notes”, which shares the latest news in the automotive electronics industry, as well as development notes, learning notes, and related experiences.Follow the public account to obtain relevant documents.
