In SoC (System-on-Chip) design, clock design is a core and highly challenging task that directly affects the chip’s performance, power consumption, reliability, and testability. A robust SoC clock architecture needs to consider multiple factors.
Core Objectives. Functional Correctness: Ensure all modules operate on the correct clock edge, meeting timing constraints. High Performance: Provide clock frequencies that meet critical path requirements while minimizing clock delay and jitter. Low Power Consumption: Significantly reduce dynamic power consumption through fine clock gating and dynamic frequency adjustment (clock network power can account for 30%-40%). High Reliability: Manage clock domain crossing (CDC) to prevent metastability; ensure clock quality (low jitter, low skew); provide fault tolerance mechanisms (such as clock monitoring and redundancy). Flexibility/Configurability: Support dynamic voltage frequency scaling (DVFS), multiple operating modes, and clock switching. Testability: Support ATPG scan testing, built-in self-test (BIST), and clock control testing. Physical Implementability: Consider layout and routing (P&R) constraints to ensure the clock tree meets timing, power, and physical design rules.
Key Design Methods. Identify Clock Domains: Clearly define all independent clock sources in the SoC and the logic areas driven by their derived clocks (divided, multiplied, gated). Each independent clock source and its valid derived clocks define a clock domain. Minimize Clock Domain Count: Reduce the number of clock domains as much as possible while meeting functional requirements to simplify CDC design and timing convergence. Reasonable Partitioning: Partition based on functional modules, performance requirements, and power domains. High-speed cores, low-speed peripherals, analog interfaces, and standby logic typically belong to different domains. On-chip Oscillator: Used for low-frequency, low-precision requirements (such as standby clocks). External Crystal + PLL: The mainstream solution. PLL provides a high-precision, low-jitter main clock and can perform frequency multiplication, division, and phase adjustment. DLL: Used to eliminate clock path delays, commonly found in high-performance interfaces. Clock Distribution Network: Use balanced H-Tree or Mesh structures to distribute clocks from the source (PLL output) to the entrances of various clock domains (Clock Gating Cells or Local Buffers). The goal is low skew, low latency, and low power consumption. Global Clock Tree: Composed of dedicated low-skew clock buffers and routing resources, serving major high-speed domains. Local Clock Tree: Built from standard cell buffers within modules or sub-regions, optimizing local skew and power consumption.
Clock Gating. Hierarchical Gating: Insert gating cells at different levels. Module Level: Turn off the clock for entire non-working modules. Sub-module/Functional Unit Level: Turn off the clock for finer-grained logic. Register Level: The finest granularity, based on register enable signals gating (usually automatically inserted by synthesis tools). Gating Strategy: Insert gating based on functional state, data validity, and low-power mode requirements. Gating Cell Selection: Use low-power, integrated latch ICG cells to avoid glitches.
Dynamic Voltage Frequency Scaling. Integrate multiple PLLs/DLLs: Provide independently adjustable clock sources for different performance requirements. Clock Switching Logic: Design safe, glitch-free clock switching circuits (using MUX and synchronizers) to support runtime frequency switching (DFS). Voltage Regulation Coordination: Frequency switching is usually accompanied by voltage regulation (implemented by PMIC or on-chip LDO), ensuring that the operating voltage meets timing requirements at the target frequency.
Clock Domain Crossing Management. Synchronizers: Synchronizers must be inserted on asynchronous CDC paths (usually two-stage or multi-stage flip-flops). Choose the correct type of synchronizer (standard dual flip-flop, handshake synchronizer, FIFO asynchronous, pulse synchronizer, etc.). CDC Verification: Use specialized CDC verification tools (such as JasperGold, VC SpyGlass CDC) for thorough checks to ensure all asynchronous paths are correctly synchronized, avoiding metastability propagation and data loss/corruption. This is a key guarantee of functional correctness. Data Consistency: For multi-bit bus CDC, techniques such as Gray code, handshake + FIFO, or Mutex should be used to ensure data consistency.
Low Jitter Design. PLL Design Optimization: Choose low-noise PLL architectures, optimize loop filters and VCO. Power Integrity: Provide clean, stable power to PLLs and clock buffers (using LDOs, decoupling capacitors, and power isolation). Crosstalk Control: Avoid long parallel routing of clock lines with high transition rate signal lines during routing, using shielding. Clock Buffer Selection: Use low-noise, high PSRR clock buffers.
Testability Design. Scan Test Clock: Reuse functional clocks or design dedicated paths for scan shifting and capture modes. Typically requires a scan_enable signal to control the clock MUX. ATE Clock Access: Ensure critical clocks (PLL output, test clocks) can be controlled and observed by ATE. Clock Control Logic Testing: Ensure that clock gating, multiplexers, dividers, and other control logic are testable. BIST Clock: Provide the necessary test clocks for memory BIST, logic BIST, etc.
Redundancy and Fault Tolerance. Critical Clock Redundancy: For extremely important clock domains (such as system reference clocks), redundant PLLs or clock paths can be used. Clock Monitoring: Integrated circuits monitor clock frequency, presence (Clock Presence), and lock status (PLL Lock), triggering error handling or safety state machines. Watchdog Timer: Use an independent clock source to monitor whether the system’s main clock is operating normally.
Design Process Recommendations. Architecture Planning: Define all clock requirements (frequency, relationships, gating strategies, DVFS schemes, testing requirements). RTL Design: Clearly define clock domains, correctly implement clock gating, division, switching, and CDC synchronization logic. Functional Simulation: Verify the functional correctness of clock control logic and CDC logic. CDC Verification: Use specialized tools for thorough CDC rule checks and verification. Synthesis: Insert hierarchical clock gating and define clock constraints. DFT Insertion and Verification: Integrate test clock structures and verify. Physical Implementation. Layout: Reasonably place clock sources (PLL), clock buffers, and macro modules, considering clock routing. Clock Tree Synthesis: Build optimized clock trees. Routing: Prioritize clock line routing, optimize topology, and control crosstalk. Timing/Power/Noise Sign-off: Conduct rigorous analysis under various conditions. Post-simulation and ECO: Perform post-simulation with delays if necessary, executing engineering changes.
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